AM79C850KCW AMD [Advanced Micro Devices], AM79C850KCW Datasheet - Page 48

• Manufacturer Part Number: AM79C850KCW
• Description: SUPERNET-R 3
• Manufacturer: AMD [Advanced Micro Devices]

Parity Generation and Checking
The SUPERNET 3 will have the following sequence of
parity generation and checking:
Transmit Path:
The parity, (even or odd) will be checked at the buffer
memory interface (BDP pins). Even parity will be
regenerated at the MAC—external PHY interface.
Receive Path:
Parity (even or odd) will be generated at the buffer
memory interface. Even parity will be checked at the
external PHY (R Bus) interface, if ENA_PAR_CHK
(bit 10) in PLC_CNTRL_A register is set.
48
AMD
EARV1
EARV2
EACB
EAA0
EAA1
EAS
Figure 17. Buffer Memory Queue Organization
ASYNCHRONOUS QUEUE 0
ASYNCHRONOUS QUEUE 1
SYNCHRONOUS QUEUE
SPECIAL FRAME AREA
P R E L I M I N A R Y
RECEIVE QUEUE 1
RECEIVE QUEUE 2
(TRANSMIT)
(TRANSMIT)
(TRANSMIT)
SUPERNET 3
Node Processor Synchronous Mode
Operation
The NPMODE pin (external pin) must be strapped
high to select SUPERNET 3 synchronous operation
and
asynchronous operation.
There are two possible methods of synchronous
operation of the SUPERNET 3:
1. BMCLK frequency equals BCLK frequency. (i.e.
2. BMCLK operates at twice BCLK (i.e. BMCLK =
12.5 MHz), and both clocks must be in phase.
25 MHz), and both clocks must be in phase.
strapped
low
to
SACL
SABC
RPR1
SWPR1
WPR1
RPXS
SWPXS
WPXS
RPXA0
SWPXA0
WPXA0
RPXA1
SWPXA1
WPXA1
RPX2
SWPX2
WPR2
select
19574A-18
SUPERNET
3