CYIL1SM0300AA CYPRESS [Cypress Semiconductor], CYIL1SM0300AA Datasheet - Page 19

• Manufacturer Part Number: CYIL1SM0300AA
• Description: LUPA-300 CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-00371 Rev. *D
Voffset <7:0>
This register is the input for the on-chip DAC, which generates
the Voffset supply used by the PGA. When the register is
"00000000" it will set a Voffset of 2.5V. When the register is
11111111 then it will set a Voffset of 0V. This means that the
minimum step you can take with the Voffset register is 9.8
mV/bit (2.5V/256bits).
For more information, see section 3.4
Ana_in_ADC <11:0>
This register sets the different paths that can be used as the
ADC input (mainly for testing and debugging). The register
consists of several "sub-registers".
Sel_test_path (4 bits)
These bits select the analog test path of the ADC.
0000: No analog test path selected (default)
0001: Path of pixel 1 selected
0010: Path of pixel 2 selected
Sel_path (4 bits)
These bits select the analog path to the ADC.
1111: All paths selected (normal operation) - default
0000: No paths selected (enables ADC to be tested through
test paths)
0001: Path of pixel 1 selected
0010: Path of pixel 2 selected
Bypass_mux (4 bits)
These bits enable the possibility to bypass the digital 4 to 1
multiplexer.
0000: no bypass (default)
PGA_SETTING <11:0>
This register defines all parameters to set the PGA. The
register consists of different "sub-registers"
Gain_pga (4 bits)
These bits set the gain of the PGA. The following Table 16
gives an overview of the different gain settings.
Table 16.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
GAIN_PGA<3:0>
1.32
1.56
1.85
2.18
2.58
3.05
3.59
4.22
4.9
5.84
6.84
Gain
Table 16. (continued)
Unity_pga (1 bit)
This bit sets the PGA in unity amplification.
0: No unity amplification, gain settings apply
1: Unity gain amplification, gain setting are ignored (default)
Sel_uni (1 bit)
This bit selects whether or not the signal gets a 0.5 amplifi-
cation before the PGA.
0: amplification of 0.5 before PGA
1: Unity feed through (default)
Enable_analog_in (1 bit)
This bit enables/disables an analog input to the PGA.
0: analog input disabled (default)
1: analog input enabled
Enable_adc (4 bits)
These bits can separately enable/disable the different ADCs.
0000: No ADCs enabled
1111: All ADCs enabled (default)
0001: ADC 1 enabled
0010: ADC 2 enabled
Sel_calib_fast (1 bit)
Selects the fast/slow calibration of the ADC
0: slow calibration
1: fast calibration
2ADC Calibration Word <32:0>
The calibration word for the ADCs is distributed over 3
registers (13, 14 and 15). These registers all have their default
value and changing this value is not recommended. The
default register values are:
calib_adc<11:0>: 101011011111
calib_adc<23:12>: 011011011011
calib_adc<32:24>: 000011011011
Data Interface (SPI)
The serial-3-wire interface (or Serial-to-Parallel Interface)
uses a serial input to shift the data in the register buffer. When
the complete data word is shifted into the register buffer the
data word is loaded into the internal register where it is
decoded.
Below is a schematic of what the 16 bit SPI register looks like
1011
1100
1101
1110
1111
GAIN_PGA<3:0>
8.02
9.38
11.2
13.12
15.38
CYIL1SM0300AA
Gain
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