CYIL1SM0300AA CYPRESS [Cypress Semiconductor], CYIL1SM0300AA Datasheet - Page 18

• Manufacturer Part Number: CYIL1SM0300AA
• Description: LUPA-300 CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-00371 Rev. *D
0: disabled (default)
Calib_line (1bit)
This bit sets the calibration method of the PGA. Different
calibration modes can be set, at the beginning of the frame and
for every subsequent line that is read.
1: Calibration is done every line (default)
0: Calibration is done every frame (less row fixed pattern
noise)
Res2_enable (1bit)
This bit enables/disables the dual slope mode of the device.
1: Dual slope is enabled (configured according to the
RES2_TIMER register)
0: Dual slope is disabled (RES2_timer register is ignored) -
default
Res3_enable (1bit)
This bit enables/disables the triple slope mode of the device.
1: triple slope is enabled (configured according to the
RES3_TIMER register)
0: triple slope is disabled (RES3_timer register is ignored) -
default
Reverse_X (1bit)
The readout direction in X can be reversed by setting this bit
through the SPI.
1: Read direction is reversed (from right to left)
0: normal read direction (from left to right) - default
Reverse_Y (1bit)
The readout direction in Y can be reversed by setting this bit
through the SPI.
1: Read direction is reversed (from bottom to top)
0: normal read direction (from top to bottom) - default
Ndr (1 bit)
This bit enables the non destructive readout mode if desired.
1: ndr enables
0: ndr disables (default)
Start_X Register <7:0>
This register sets the start position of the readout in X direction.
In this direction there are 80 (from 0 to 79) possible start
positions (8 pixels are addressed at the same time in one clock
cycle). Keep in mind that if you put Start_X to 0 pixel 0 is being
read out. Example:
If you set 23 in the Start_X register readout will only start from
pixel 184 (8x23)
Start_Y Register <8:0>
This register sets the start position of the readout in Y direction.
In this direction there are 480 (from 0 to 479) possible start
positions. This means that the start position in Y direction can
be set on a line by line basis.
Nb_pix <7:0>
This register sets the number of pixels to read out. The number
of pixels to be read out is expressed as a number of kernels in
this register (4 pixels per kernel). This means that there are
160 possible values for the register (from 1 to 160). Example:
If you set 37 in the nb_pix register, 148 (37 x 4) pixels will be
read out.
Res1_length <11:0>
This register sets the length of the reset pulse (how long it
remains high). This length is expressed as a number of lines
(res1_length - 1). The minimum and default value of this
register is 2.
The actual time the reset is high can be calculated with the
following formula:
Reset high = (Res1_length-1) * (ROT + Nr. Pixels * clock
period)
Res2_timer <11:0>
This register defines the position of the additional reset pulse
to enable the dual slope capability. This is also defined as a
number of lines-1.
The actual time on which the additional reset is given can be
calculated with the following formula:
DS high = (Res2_timer-1) * (ROT + Nr. Pixels * clock period)
Res3_timer <11:0>
This register defines the position of the additional reset pulse
to enable the triple slope capability. This is also defined as a
number of lines - 1.
The actual time on which the additional reset is given can be
calculated with the following formula:
TS high = (Res3_timer-1) * (ROT + Nr. Pixels * clock period)
Ft_timer <11:0>
This register sets the position of the frame transfer to the
storage node in the pixel. This means that it also defines the
end of the integration time. It is also expressed as a the
number of lines - 1.
The actual time on which the frame transfer takes place can
be calculated with the following formula:
FT time = (ft_timer-1) * (ROT + Nr. Pixels * clock period)
Vcal <7:0>
This register is the input for the on-chip DAC which generates
the Vcal supply used by the PGA.
When the register is "00000000" it will set a Vcal of 2.5V. When
the register is 11111111 then it will set a Vcal of 0V. This means
that the minimum step you can take with the Vcal register is
9.8mV/bit (2.5V/256bits).
For more information, see section 3.4
Vblack <7:0>
This register is the input for the on-chip DAC which generates
the Vblack supply used by the PGA. When the register is
"00000000" it will set a Vblack of 2.5V. When the register is
11111111 then it will set a Vblack of 0V. This means that the
minimum step you can take with the Vblack register is
9.8mV/bit (2.5V/256bits).
For more information, see section 3.4
CYIL1SM0300AA
Page 18 of 36
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