CYIL1SM0300AA CYPRESS [Cypress Semiconductor], CYIL1SM0300AA Datasheet - Page 14

• Manufacturer Part Number: CYIL1SM0300AA
• Description: LUPA-300 CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-00371 Rev. *D
column amplifiers with respect to power dissipation, we need
several biasing resistors. This optimization results in an
increase of signal swing and dynamic range.
Table 12. Overview of Bias Signals
Digital Signals
Depending on the operation mode (master or slave), the pixel
array of the image sensor requires different digital control
Table 13. Overview of Digital Signals
Synchronous Shutter
In a synchronous (snapshot or global) shutter light integration
takes place on all pixels in parallel, although subsequent
readout is sequential. Figure 9 shows the integration and read
out sequence for the synchronous shutter. All pixels are light
Note
4. Each biasing signal determines the operation of a corresponding module in the sense that it controls speed and dissipation.
ADC_BIAS
PRECHARGE_BIAS
BIAS_PGA
BIAS_FAST
BIAS_SLOW
BIAS_COL
LINE_VALID
FRAME_VALID
INT_TIME_3
INT_TIME_2
INT_TIME_1
RESET_N
CLK
SPI_ENABLE
SPI_CLK
SPI_DATA
Signal Name
Signal
Connect with 10 kOhm to V
GND
Connect with 68 kOhm to V
GND
Biasing of amplifier stage. Connect with 110 kOhm to V
decouple with 100 nF to GND
Biasing of columns. Connect with 42 kOhm to V
decouple with 100 nF to GND
Biasing of columns. Connect with 1.5 MOhm to V
decouple with 100 nF to GND
Biasing of imager core. Connect with 500 kOhm to V
decouple with 100 nF to GND
Digital output
Digital output
Digital IO
Digital IO
Digital IO
Digital input
Digital input
Digital input
Digital input
Digital IO
ADC
DRIVERS
.
I/O
.
Indicates when valid data is at the outputs. Active high
Indicates when a valid frame is readout. Active high
In master mode: Output to indicate the triple slope integration time.
In slave mode: Input to control the triple slope integration time.
Active high
In master mode: Output to indicate the dual slope integration time.
In slave mode: Input to control the dual slope integration time.
Active high
In master mode: Output to indicate the integration time.
In slave mode: Input to control integration time.
Active high
Sequencer reset. Active low
Readout clock (80 MHz), sine or square clock
Enable of the SPI
Clock of the SPI. (max. 20 MHz)
Data line of the SPI. Bidirectional pin
Comment
ADC
PIX
A
A
A
A
.
.
.
.
and decouple with 100 nF to
and decouple with 100n to
signals. The function of each of the signals is shown in
Table 13:
sensitive at the same period of time. The whole pixel core is
reset simultaneously and after the integration time all pixel
values are sampled together on the storage node inside each
pixel. The pixel core is read out line by line after integration.
Note that the integration and read out cycle can occur in
DDA
DDA
and
DDA
DDA
and
Comments
and
and
ADC
Pixel array precharge
PGA
Column amplifiers
Column amplifiers
Column amplifiers
Related Module
CYIL1SM0300AA
Page 14 of 36
693 mV
567 mV
650 mV
750 mV
450 mV
508 mV
DC-Level‘
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