CYIL1SM0300AA CYPRESS [Cypress Semiconductor], CYIL1SM0300AA Datasheet - Page 17

• Manufacturer Part Number: CYIL1SM0300AA
• Description: LUPA-300 CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-00371 Rev. *D
Table 15. Internal Registers (continued)
Detailed Description of the Internal Registers
The registers should only be changed during FOT (when
frame valid is low).
These registers should only be changed during RESET_N is
low:
Sequencer Register <10:0>
The sequencer register is an 11 bit wide register that controls
all
"sub-registers".
Mastermode (1 bit)
This bit controls the selection of mastermode/slavemode. The
sequencer can operate in 2 modes: master mode and slave
mode. In master mode all the internal timing is controlled by
the sequencer, based on the SPI settings. In slave mode the
integration timing is directly controlled over three pins, the
readout timing is still controlled by the sequencer.
1: Master mode (default)
0: Slave mode
8 (1000)
9 (1001)
10 (1010)
11 (1011)
12 (1100)
13 (1101)
14 (1110)
15 (1111)
• Mastermode register
• Granularity register
of
the
Address
sequencer
settings.
7:0
7:0
7:0
11:0
4
4
4
11:0
4
1
1
1
4
1
11:0
11:0
8:0
Bits
It
contains
VCAL
VBLACK
VOFFSET
ANA_IN_ADC
sel_test_path
sel_path
bypass_mux
PGA_SETTING
gain_pga
unity_pga
sel_uni
enable_analog_in
enable_adc
sel_calib_fast
CALIB_ADC <11:0>
CALIB_ADC <23:12>
CALIB_ADC <32:24>
several
Name
Subsampling (1bit)
This
Subsampling is only possible in Y direction and follows this
pattern:
By default, the subsampling mode is disabled.
Clock granularity (2 bits)
The system clock (80 MHz) is divided several times on chip.
The clock, that drives the "snapshot" or synchronous shutter
sequencer, can be programmed using the granularity register.
The value of this register depends on the speed of your system
clock.
11: > 80 MHz
10: 40-80 MHz (default)
01: 20-40 MHz
00: < 20 MHz
Enable analog out (1 bit)
This bit enables/disables the analog output amplifier.
1: enabled
• Read one, skip one: Y0Y0Y0Y0…
bit
enables/disables
DAC input for vcal
Default <7:0>: 01001010
DAC input for vblack
Default <7:0>: 01101011
DAC input for voffset
Default <7:0>: 01010101
Activate analog ADC input
Default <11:0>: 000011110000
Selection of analog test path
Selection of normal analog path
Bypass of digital 4 to 1 mux
PGA settings
Default <11:0>: 111110110000
Gain settings PGA
PGA unity amplification
Preamplification of 0.5 (0: enabled)
Activate analog input
Put separate ADCs in standby
Select fast calibration of PGA
Calibration word of the ADCs
Default:
calib_adc<11:0>:101011011111
calib_adc<23:12>:011011011011
calib_adc<32:24>:000011011011
Description
CYIL1SM0300AA
the
subsampling
Page 17 of 36
mode.
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