AM29PDL640G AMD [Advanced Micro Devices], AM29PDL640G Datasheet
AM29PDL640G
Related parts for AM29PDL640G
AM29PDL640G Summary of contents
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... Data Sheet This product has been retired and is not available for designs. For new and current designs, S29PL064J supersedes Am29PDL640G and is the factory-recommended migration path. Please refer to the S29PL064J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. ...
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... Control TM This product has been retired and is not available for designs. For new and current designs, S29PL064J supersedes Am29PDL640G and is the factory-recommended migration path. Please DISTINCTIVE CHARACTERISTICS refer to the S29PL064J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. ...
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... GENERAL DESCRIPTION The Am29PDL640G Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device orga- nized as 4 Mwords. The device is offered in 63- or 80-ball Fine-pitch BGA packages. The word-wide data (x16) ap- pears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers not required for write or erase operations ...
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... Table 5. Bank Address ....................................................................15 TM Table 6. SecSi Sector Addresses ...............................................15 Autoselect Mode..................................................................... 15 Table 7. Autoselect Codes (High Voltage Method) ........................16 Table 8. Am29PDL640G Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................................16 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 17 Persistent Sector Protection ................................................... 17 Persistent Protection Bit (PPB) ............................................... 17 Persistent Protection Bit Lock (PPB Lock) ............................. 17 Dynamic Protection Bit (DYB) ................................................ 17 Table 9 ...
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... Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 54 Erase And Programming Performance Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 55 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 55 Data Retention Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 56 FBE080—80-Ball Fine-pitch Ball Grid Array package .............................................................. 56 FBE063—63-Ball Fine-pitch Ball Grid Array package .............................................................. 57 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58 Am29PDL640G December 13, 2005 ...
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... 1.65–1. Sector Switches Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic Y-Decoder STB Timer X-Decoder Am29PDL640G Am29PDL640G DQ15–DQ0 V IO Input/Output Buffers STB ...
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... RESET# STATE WE# CONTROL CE# & WP#/ACC COMMAND REGISTER DQ0–DQ15 A21–A0 Mux OE# Bank A Bank A Address X-Decoder Bank B Address Bank B X-Decoder Status Control X-Decoder Bank C Bank C Address X-Decoder Bank D Address Bank D Am29PDL640G DQ15–DQ0 Mux December 13, 2005 ...
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... G4 H4 A18 A20 DQ2 DQ10 DQ0 DQ8 CE Am29PDL640G DQ15 DQ13 DQ6 DQ4 DQ11 DQ3 J3 K3 DQ9 DQ1 ...
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... H5 V A21 A19 DQ5 DQ12 A18 A20 DQ2 DQ10 DQ11 DQ0 DQ8 DQ9 CE# OE# Am29PDL640G L8 M8 NC* NC NC* NC DQ6 J5 K5 DQ4 DQ3 J3 K3 DQ1 NC* ...
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... V = Output Buffer Power Supply (not avail- IO able in 63-ball FBGA package Device Ground Pin Not Connected Internally December 13, 2005 LOGIC SYMBOL 22 A21–A0 CE# OE# WE# WP#/ACC RESET# V (N/A 63-ball FBGA) IO Am29PDL640G 16 DQ15–DQ0 RY/BY# 9 ...
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... Consult the local AMD sales office to con- IO (ns) Range firm availability of specific valid combinations and to check on newly released combinations. 65 2.7– Note: For the Am29PDL640G, the last digit of the speed indicator 3 specifies V range. Speed grades ending in 3 (such as 73,83) indicate Volt V range ...
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... The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the Table 1. Am29PDL640G Device Bus Operations Operation Read Write Standby ...
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... When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. Am29PDL640G AC section contains timing specification on this pin, the device auto- HH ...
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... SET# pin returns to V Refer to the rameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input disabled. The output pins (except for RY/BY#) are placed in the high impedance state. Table 4. Am29PDL640G Sector Architecture Bank Sector + ACC SA0 SA1 ...
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... Table 4. Am29PDL640G Sector Architecture Sector Sector Bank Sector Address Size A21–A12 (Kwords) SA23 0010000xxx 32 SA24 0010001xxx 32 SA25 0010010xxx 32 SA26 0010011xxx 32 SA27 0010100xxx 32 SA28 0010101xxx 32 SA29 0010110xxx 32 SA30 0010111xxx 32 SA31 0011000xxx 32 SA32 0011001xxx 32 SA33 0011010xxx 32 SA34 0011011xxx 32 SA35 0011000xxx 32 SA36 0011101xxx ...
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... Table 4. Am29PDL640G Sector Architecture Sector Sector Bank Sector Address Size A21–A12 (Kwords) SA119 1110000xxx 32 SA120 1110001xxx 32 SA121 1110010xxx 32 SA122 1110011xxx 32 SA123 1110100xxx 32 SA124 1110101xxx 32 SA125 1110110xxx 32 SA126 1110111xxx 32 SA127 1111000xxx 32 SA128 1111001xxx 32 SA129 1111010xxx 32 SA130 1111011xxx 32 SA131 1111100xxx 32 SA132 1111101xxx ...
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... Verification SecSi Indicator Bit (DQ7) Legend Logic Low = Logic High = V IL Note: The autoselect codes may also be accessed in-system via command sequences. Table 8. Am29PDL640G Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A21–A12 SA0 0000000000 SA1 0000000001 SA2 0000000010 ...
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... SECTOR PROTECTION The Am29PDL640G features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires ...
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... The Password Sector Protection Mode method allows . IL an even higher level of security than the Persistent Sector Protection Mode. There are two main differ- ences between the Persistent Sector Protection and the Password Sector Protection Mode: Am29PDL640G Sector State Unprotected—PPB and DYB are 0 changeable Unprotected—PPB not 1 ...
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... Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a “1” when the Password Mode Lock Bit is not set. Am29PDL640G High Voltage Sector on the WP#/ACC pin, the de- IL ...
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... The proce- dure requires high voltage (V RESET# pin. Refer to Figure Note: for details on this procedure. Note that for sector unprotect, all unpro- tected sectors must first be protected prior to the first sector write cycle. Am29PDL640G ) to be placed on the ID December 13, 2005 ...
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... No Yes PLSCNT = 1000? Yes Remove V from RESET# Write reset command Sector Unprotect complete Device failed Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms Am29PDL640G START PLSCNT = 1 RESET Wait 4 μs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? ...
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... Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note Am29PDL640G December 13, 2005 ...
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... The system can read CFI information at the addresses given in Tables 10–13. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is exe- Am29PDL640G , the device does not ac- LKO is greater than V CC LKO ...
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... For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alterna- tively, contact an AMD representative for copies of these documents. Am29PDL640G December 13, 2005 ...
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... Max. timeout for byte/word write 2 times typical N Max. timeout for buffer write 2 times typical Max. timeout per individual block erase 2 N Max. timeout for full chip erase 2 times typical (00h = not supported) Am29PDL640G N µs N µ s (00h = not supported times typical ...
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... CFI specification or CFI publication 100) Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) Am29PDL640G N December 13, 2005 ...
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... Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported Supported Bank Organization 00 = Data at 4Ah is zero Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 Am29PDL640G 27 ...
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... Table 4 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Am29PDL640G December 13, 2005 ...
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... In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the table in the AC Characteristics section for parameters, and Figure 15 for timing diagrams. Am29PDL640G any operation HH Erase and Program Operations 29 ...
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... WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the sec- bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read Am29PDL640G Erase and Program Operations ta- December 13, 2005 ...
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... Four Password Program commands are required to program the password. The system must section for more enter the unlock cycle, password program command (38h) and the program address/data for each portion Am29PDL640G Autoselect Mode and Autoselect Com- sections for details. ...
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... The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the DYB Write command is accomplished by writing the Read/Reset command. Am29PDL640G -level SecSi Sector CC December 13, 2005 ...
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... Sector Protection Status Command The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sec- tor Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group. Am29PDL640G 33 ...
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... Command is valid when device is ready to read array data or when device is in autoselect mode. 14. WP#/ACC must 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array. Am29PDL640G Addr Data Addr Data Addr ...
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... Immediately following successful unlock, write the SecSi Sector Exit command before attempting to verify, program, or erase the PPBs. 18. Immediately following the PPB Lock Status command write the SecSi Sector Exit command before attempting to verify, program, or erase the PPBs. Am29PDL640G Data Addr Data Addr XX ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm Am29PDL640G section shows the Data# Yes No Yes Yes ...
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... Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 7. Toggle Bit Algorithm Am29PDL640G DQ2: Toggle Bit II. START Read Byte (DQ7– ...
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... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 16 shows the status of DQ3 relative to the other status bits. Am29PDL640G Sector Erase Command December 13, 2005 ...
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... The device outputs array data if the system addresses a non-busy bank. December 13, 2005 Table 16. Write Operation Status DQ7 DQ5 (Note 2) DQ6 (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle Am29PDL640G DQ2 DQ3 (Note 2) RY/BY# 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data 1 ...
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... (see Note 1.65–1. 2.7–3 Note: For all AC and DC specifications, V AMD for other V options. IO Operating ranges define those limits between which the functionality of the device is guaranteed. Am29PDL640G contact IO CC December 13, 2005 ...
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... 2.7–3 min IO 4. Automatic sleep mode enables the low power mode when addresses remain stable for t current is 200 nA CCmax 5. Not 100% tested. Am29PDL640G Min Typ Max Unit ±1.0 µA 35 µA ±1.0 µ ...
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... Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am29PDL640G 63, 98 73, 83 Unit 1 TTL gate 0.0–3 ...
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... Test Setup CE Read Toggle and Data# Polling . Addresses Stable t ACC OEH t CE HIGH Z Valid Data Figure 12. Read Operation Timings Am29PDL640G Speed Options Min Max Max Max Max ...
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... AC CHARACTERISTICS A21-A3 A2-A0 Data CE# OE# Figure 13. Page Read Operation Timings Same Page PACC PACC t ACC Qa Qb Am29PDL640G Ad t PACC Qc Qd December 13, 2005 ...
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... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 14. Reset Timings Am29PDL640G All Speed Options Unit 20 µs 500 ns 500 µ ...
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... See the “Erase And Programming Performance” section for more information Min 65 Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max Am29PDL640G Speed Options Unit ...
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... WPH A0h t BUSY is the true data at the program address. OUT Figure 15. Program Operation Timings Am29PDL640G Read Status Data (last two cycles WHWH1 D Status OUT VHH 47 ...
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... Note sector address (for Sector Erase Valid Address for reading status data (see “Write Operation Status” Figure 17. Chip/Sector Erase Operation Timings 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY Am29PDL640G Read Status Data WHWH2 Status D OUT t RB December 13, 2005 ...
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... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am29PDL640G Valid PA Valid CPH Valid Valid In In CE# Controlled Write Cycles VA High Z True Valid Data High Z True Valid Data ...
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... AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 21. DQ2 vs. DQ6 Am29PDL640G Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read December 13, 2005 ...
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... VIDR CE# WE# RY/BY# Figure 22. Temporary Sector Unprotect Timing Diagram December 13, 2005 Min Min Min Min Program or Erase Command Sequence t RSP Am29PDL640G All Speed Options Unit 500 ns 250 ns 4 µs 4 µ VIDR ...
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... For sector protect For sector unprotect Figure 23. Sector/Sector Block Protect and Valid* Valid* 60h Sector Group Protect: 150 µs Sector Group Unprotect Unprotect Timing Diagram Am29PDL640G Valid* Verify 40h Status December 13, 2005 ...
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... See the “Erase And Programming Performance” section for more information. December 13, 2005 Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Am29PDL640G Speed Options Unit ...
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... SA for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am29PDL640G PA DQ7# D OUT December 13, 2005 ...
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... V, 1,000,000 cycles. CC –100 mA = 3.0 V, one pin at a time. CC Test Setup OUT V IN Test Conditions Am29PDL640G Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec Excludes system level µs overhead (Note 5) µs sec , 1,000,000 cycles. Additionally, CC Min Max – ...
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... WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW e/2 8. "+" IN THE PACKAGE DRAWING INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 FOR PACKAGE THICKNESS, "A" IS THE CONTROLLING DIMENSION CORNER TO BE IDENTIFIED BY CHAMFER, INK MARK, METALLIZED MARKINGS INDENTION OR OTHER MEANS. Am29PDL640G ...
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... PHYSICAL DIMENSIONS FBE063—63-Ball Fine-pitch Ball Grid Array package December 13, 2005 Am29PDL640G Dwg rev AF; 10/99 57 ...
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... Connection Diagram Added Note. Removed the 64-ball Fortified BGA connection dia- gram. Ordering Information Removed the Extended temperature range. Removed the PC package type. Table 1. Am29PDL640G Device Bus Operations and Standby Mode ± 0 Changed V CC Table 14. Memory Array Command Definitions Deleted Configuration Register Verify and Write from table ...
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... This product has been retired and is not available for designs. For new and current designs, S29PL064J su- persedes Am29PDL640G and is the factory-recom S29PL064J datasheet for specifications and ordering information ...