CD4030CN Fairchild Semiconductor, CD4030CN Datasheet
CD4030CN
Manufacturer Part Number
CD4030CN
Description
IC GATE OR QUAD EXCLUSIVE 14-DIP
Manufacturer
Fairchild Semiconductor
Series
4000r
Datasheet
1.CD4030CN.pdf
(5 pages)
Specifications of CD4030CN
Logic Type
XOR (Exclusive OR)
Number Of Inputs
2
Number Of Circuits
4
Voltage - Supply
3 V ~ 15 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Through Hole
Package / Case
14-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Output High, Low
-
Other names
4030
4030A
CD4030
4030A
CD4030
© 2002 Fairchild Semiconductor Corporation
CD4030CSJ
CD4030CN
CD4030C
Quad EXCLUSIVE-OR Gate
General Description
The CD4030C EXCLUSIVE-OR gates are monolithic com-
plementary MOS (CMOS) integrated circuits constructed
with N- and P-channel enhancement mode transistors. All
inputs are protected against static discharge with diodes to
V
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Order Number
DD
and V
SS
.
Package Number
M14D
N14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS005961
Features
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Industrial controls
• Remote metering
• Computers
Truth Table
1
0
Wide supply voltage range:
Low power: 100 nW (typ.)
Medium speed operation:
t
High noise immunity
HIGH Level
LOW Level
PHL
Package Description
t
PLH
A
0
1
0
1
40 ns (typ.) at C
0.45 V
B
0
0
1
1
October 1987
Revised April 2002
L
3.0V to 15V
CC
15 pF, 10V supply
(typ.)
www.fairchildsemi.com
J
0
1
1
0
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CD4030CN Summary of contents
Page 1
... Package Number CD4030CSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4030CN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram © ...
Page 2
Logic Diagram www.fairchildsemi.com 2 ...
Page 3
Absolute Maximum Ratings Voltage at Any Pin (Note Operating Temperature Range Storage Temperature Range Power Dissipation ( Dual-In-Line Small Outline Operating V Range V 3. Lead Temperature (Soldering, ...
Page 4
Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M14D 4 ...
Page 5
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...