EVAL-SSM2518Z AD [Analog Devices], EVAL-SSM2518Z Datasheet - Page 36

• Manufacturer Part Number: EVAL-SSM2518Z
• Description: Digital Input Stereo, 2 W, Class-D
• Manufacturer: AD [Analog Devices]

DRC CONTROL 1 REGISTER
Address: 0x0A, Reset: 0x7C, Name: DRC_Control_1
Table 23. Bit Descriptions for DRC_Control_1
Bits
7
6
5
4
3
2
[1:0]
SSM2518
Bit Name
RESERVED
PRE_VOL
LIM_EN
COMP_EN
EXP_EN
NG_EN
DRC_EN
Settings
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Description
Reserved.
DRC Placement. This determines the placement of the DRC block in the
signal chain. When placed before the volume control, the thresholds are
relative to the input signal. When placed after the volume control, the
thresholds are relative to the output signal level. All thresholds are 6 dB
higher when placed after the volume control.
DRC operates after the volume control
DRC operates before the volume control
Limiter Enable. With the limiter enabled, the DRC_LT threshold (Bits[7:4] in
Register 0x0C) must be set.
Limiter disabled
Limiter enabled
Compressor Enable. With the compressor enabled, the DRC_CT and
DRC_SMAX thresholds (Bits[3:0] in Register 0x0C and Bits[7:4] in
Register 0x0E) must be set.
Compressor disabled
Compressor enabled
Expander Enable. With the expander enabled, the DRC_ET and DRC_SMIN
threshold values (Bits[7:4] in Register 0x0D and Bits[3:0] in Register 0x0E)
must be set.
Expander disabled
Expander enabled
Noise Gate Enable. With the noise gate enabled, the DRC_NT threshold
value (Bits[3:0] in Register 0x0D) must be set.
Noise gate disabled
Noise gate enabled
Master DRC Enable. This must be enabled for any of the DRC features to
function.
DRC disabled
Left channel DRC enabled
Right channel DRC enabled
Left and right channel DRC enabled
Rev. A | Page 36 of 48
Data Sheet
Reset
0x0
0x1
0x1
0x1
0x1
0x1
0x0
Access
RW
RW
RW
RW
RW
RW
RW