EVAL-SSM2518Z AD [Analog Devices], EVAL-SSM2518Z Datasheet - Page 29

• Manufacturer Part Number: EVAL-SSM2518Z
• Description: Digital Input Stereo, 2 W, Class-D
• Manufacturer: AD [Analog Devices]

Data Sheet
SERIAL AUDIO INTERFACE CONTROL REGISTER
Address: 0x03, Reset: 0x00, Name: Serial_Interface_Control
Table 16. Bit Descriptions for Serial_Interface_Control
Bits
7
6
5
4
[3:2]
1
0
Bit Name
BCLK_GEN
LRCLK_MODE
LRCLK_POL
SAI_MSB
SLOT_WIDTH
BCLK_EDGE
RESERVED
Settings
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Description
Internal BCLK Generator Enable.
Bit clock from BCLK pin is used
Internally generated bit clock is used
LRCLK Shape Selection. Required only for TDM modes.
50% duty cycle
1-bit pulse
LRCLK Polarity.
Rising edge (normal)
Falling edge (inverted)
Serial Data Bit Order.
MSB first
LSB first
TDM Slot Width. Required only for TDM modes.
32 BCLK cycles per slot
24 BCLK cycles per slot
16 BCLK cycles per slot
Reserved
BCLK Active Edge.
Rising BCLK edge used
Falling BCLK edge used
Reserved.
Rev. A | Page 29 of 48
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
SSM2518
Access
RW
RW
RW
RW
RW
RW
RW