EVAL-SSM2518Z AD [Analog Devices], EVAL-SSM2518Z Datasheet - Page 22

• Manufacturer Part Number: EVAL-SSM2518Z
• Description: Digital Input Stereo, 2 W, Class-D
• Manufacturer: AD [Analog Devices]

I
OVERVIEW
The
processor bus driving multiple peripherals. Two pins, serial data
(SDA) and serial clock (SCL), carry information between the
SSM2518
is always a slave on the bus, meaning it cannot initiate a data
transfer. Each slave device is recognized by a unique device
address. The device address byte format is shown in Figure 31.
The address resides in the first seven bits of the I
LSB of this byte sets either a read or write operation.
Logic Level 1 corresponds to a read operation, and Logic Level 0
corresponds to a write operation. The full byte addresses are
shown in Figure 3, where the subaddresses are automatically
incremented at word boundaries and can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically after a single word write
unless a stop condition is encountered. A data transfer is always
terminated by a stop condition.
Both SDA and SCL should have a 2.2 kΩ pull-up resistor on the
lines connected to them.
Addressing
Initially, each device on the I
monitoring the SDA and SCL lines for a start condition and
the proper address. The I
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an
address/data stream follows. All devices on the bus respond to
the start condition and shift the next eight bits (the 7-bit
address plus the R/ W bit) MSB first. The device that recognizes
the transmitted address responds by pulling the data line low
during the ninth clock pulse. The device address is determined
by the state of the ADDR pin. This ninth bit is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and return to the idle condition. The R/ W bit
determines the direction of the data. A Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral, whereas a Logic 1 means that the master reads
information from the peripheral after writing the subaddress
and repeating the start address. A data transfer takes place until
a stop condition is encountered. A stop condition occurs when
SDA transitions from low to high while SCL is held high. The
timing for the I
SSM2518
2
C CONFIGURATION INTERFACE
SSM2518
BIT 0
0
and the system I
BIT 1
1
supports a 2-wire serial (I
Figure 31. I
2
C port is shown in
BIT 2
1
2
C Device Address Byte Format
2
BIT 3
C master initiates a data transfer by
2
0
C master controller. The
2
C bus is in an idle state,
BIT 4
1
Figure 3
ADDR
BIT 5
2
C-compatible) micro-
.
BIT 6
0
2
C write. The
BIT 7
R/W
SSM2518
Rev. A | Page 22 of 48
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the
jumps to the idle condition. During a given SCL high period,
the user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the
not issue an acknowledge and returns to the idle condition. If
the user exceeds the highest subaddress while in auto-increment
mode, one of two actions is taken. In read mode, the
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse of SCL. If the highest subaddress
location is reached while in write mode, the data for the invalid
byte is not loaded into any subaddress register, a no acknowledge
is issued by the SSM2518, and the part returns to the idle
condition.
I
Figure 33 shows the timing of a single word write operation.
Every ninth clock, the
pulling SDA low.
Figure 34 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The
subaddress register every byte because the requested subaddress
corresponds to a register or memory area with a byte word
length.
The timing of a single word read operation is shown in
Figure 35. Note that the first R/ W bit is 0, indicating a write
operation. This is because the subaddress still needs to be
written to set up the internal address. After the
acknowledges the receipt of the subaddress, the master must
issue a repeated start command followed by the chip address
byte with the R/
SDA to reverse and begin driving data back to the master. The
master then responds every ninth pulse with an acknowledge
pulse to the
Figure 36 shows the timing of a burst mode read sequence. This
figure shows an example where the target destination registers
are two bytes. The
register every byte because the requested subaddress corresponds
to a register or memory area with a byte word length.
2
C Read and Write Operations
SSM2518
W bit set to 1 (read). This causes the
SSM2518
.
SSM2518
SSM2518
knows to increment its subaddress
issues an acknowledge by
knows to increment its
SSM2518
Data Sheet
SSM2518
SSM2518
immediately
SSM2518
SSM2518
does