EVAL-CONTROLBRD2 AD [Analog Devices], EVAL-CONTROLBRD2 Datasheet - Page 3

• Manufacturer Part Number: EVAL-CONTROLBRD2
• Description: Differential Input, 1MSPS, 12-Bit ADC in ?SO-8 and S0-8
• Manufacturer: AD [Analog Devices]

AD7450 - TIMING SPECIFICATIONS
Parameter
POWER REQUIREMENTS
N O T E S
1
2
3
4
5
6
7
8
8
10
Specifications subject to change without notice.
REV. PrJ
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
Temperature ranges as follows: A, B Versions: –40°C to +85°C.
See ‘Terminology’ section.
Common Mode Voltage.
Because the input span of V
The reference is functional from 100mV and for 5V supplies it can range up to TBDV (see ‘Reference Section’).
The reference is functional from 100mV and for 3V supplies it can range up to 2.2V (see ‘Reference Section’).
Sample tested @ +25°C to ensure compliance.
See POWER VERSUS THROUGHPUT RATE section.
T
specified in Figure 8.
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
See Figure 1 and the “Serial Interface” section.
Common Mode Voltage.
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
an output to cross 0.4 V or 2.0 V for V
t
ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
Measured with a midscale DC input.
8
CONVERT
QUIET
See ‘Power-up Time’ Section.
SCLK
1
5
6
2
3
4
7
8
POWER-UP
CONVERT
5
5
6
V
I
Power Dissipation
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured num-
D D
D D
Normal Mode(Static)
Normal Mode (Operational)
Full Power-Down Mode
Normal Mode (Operational)
Full Power-Down
8 , 1 0
4
+ T
7
QUIET
+3V
10
15
16 x t
1.07
50
10
10
20
40
0.4 t
0.4 t
10
10
45
T B D
Limit at T
(See ‘Serial Interface Section’)
SCLK
SCLK
SCLK
The input signal can be centered on any choice of dc Common Mode Voltage as long as this value is in the range
IN+
MIN
and V
PRELIMINARY TECHNICAL DATA
10
18
16 x t
0.88
50
10
10
20
40
0.4 t
0.4 t
10
10
45
T B D
, T
+5V
IN-
MAX
SCLK
SCLK
DD
are both V
SCLK
= 3 V.
A Version
3/5
1
2.6
2
6
5
3
1
13
kHz min
MHz max
µs max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
REF
Units
, and they are 180° out of phase, the differential voltage is 2 x V
1
B Version
Description
Power-Up Time from Full Power-Down
t
SCLK = 15MHz, 18MHz
Minimum Quiet Time between the End of a Serial Read and the
Next Falling Edge of
Minimum
Delay from
Data Access Time After SCLK Falling Edge
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Edge to Data Valid Hold Time
SCLK Falling Edge to SDATA 3-State Enabled
SCLK Falling Edge to SDATA 3-State Enabled
3/5
1
2.6
2
1
13
6
5
3
SCLK
falling Edge to SCLK Falling Edge Setup Time
– 3 –
= 1/f
1,2
1
SCLK
Vmin/max
mA typ
mA max
mA max
µA max
mW max
mW max
µW max
µW max
( V
V
V
Units
DD
CM
DD
Pulsewidth
= 4.75V to 5.25V, f
3
= V
= 2.7V to 3.3V, f
Falling Edge Until SDATA 3-State Disabled
REF
; T
A
Range: 3 V ± 10%; 5 V ± 5%
V
V
V
SCLK On or Off
V
V
V
V
= T
DD
DD
DD
DD
DD
DD
DD
DD
MIN
Test Conditions/Comments
=5 V. f
) and timed from a voltage level of 1.6 Volts.
=3 V/5 V. SCLK On or Off
=3 V. f
=5 V. SCLK On or Off
=3 V. SCLK On or Off
= 5 V. f
= 3 V. f
to T
SCLK
SCLK
MAX
= 15MHz, f
= 18MHz, f
, unless otherwise noted.)
SAMPLE
SAMPLE
SAMPLE
SAMPLE
=1MSPS
=833kSPS
=1MSPS
=833kSPS
S
S
REF
= 833kHz, V
= 1MHz, V
DD
.
= 5 V and time for
8
, quoted in the
AD7450
REF
REF
= 2.5 V;
= 1.25 V;