EVAL-CONTROLBRD2 AD [Analog Devices], EVAL-CONTROLBRD2 Datasheet - Page 11

• Manufacturer Part Number: EVAL-CONTROLBRD2
• Description: Differential Input, 1MSPS, 12-Bit ADC in ?SO-8 and S0-8
• Manufacturer: AD [Analog Devices]

REV. PrJ
TPC 17 shows the Common Mode Rejection Ratio versus
supply ripple frequency for the AD7450 for both V
5V and 3 V. Here a 200mV p-p sine wave is coupled onto
the Common Mode Voltage of V
CIRCUIT INFORMATION
The AD7450 is a fast, low power, single supply, 12-bit
successive approximation analog-to-digital converter
(ADC). It can operate with a 5 V and 3V power supply
and is capable of throughput rates up to 1MSPS and
833kSPS when supplied with a 18MHz or 15MHz clock
respectively. This part requires an external reference to be
applied to the V
chosen depending on the power supply and to suit the
application.
When operated with a 5 V supply, the maximum reference
that can be applied to the part is 2.5 V and when operated
with a 3 V supply, the maximum reference that can be
applied to the part is 2.2 V. (See ‘Reference Section’).
The AD7450 has an on-chip differential track and hold
amplifier, a successive approximation (SAR) ADC and a
serial interface, housed in either an 8-lead SOIC or
µSOIC package.
from the part and also provides the clock source for the
successive-approximation ADC.
power-down option for reduced power consumption be-
tween conversions.
implemented across the standard serial interface as de-
scribed in the ‘Modes of Operation’ section.
CONVERTER OPERATION
The AD7450 is a successive approximation ADC based
around two capacitive DACs. Figures 3 and 4 show sim-
plified schematics of the ADC in Acquisition and
Conversion phase respectively.
Control Logic, a SAR and two capacitive DACs.
TPC 17. CMRR versus Frequency for V
90
80
70
60
50
40
30
20
10
0
10
REF
The serial clock input accesses data
pin, with the value of the reference
The power-down feature is
100
Frequency (kHz)
PRELIMINARY TECHNICAL DATA
The ADC comprises of
IN+
The AD7450 features a
and V
1000
VDD = 3 V
DD
IN-
VDD = 5 V
= 5V and 3 V
.
DD
In
10000
=
–11–
figure 3 (acquisition phase), SW3 is closed and SW1 and
SW2 are in position A, the comparator is held in a bal-
anced condition and the sampling capacitor arrays acquire
the differential signal on the input.
V IN+
When the ADC starts a conversion (figure 4), SW3 will
open and SW1 and SW2 will move to position B, causing
the comparator to become unbalanced. Both inputs are
disconnected once the conversion begins.
Logic and the charge redistribution DACs are used to add
and subtract fixed amounts of charge from the sampling
capacitor arrays to bring the comparator back into a bal-
anced condition. When the comparator is rebalanced, the
conversion is complete.
ADC’s output code. The output impedances of the
sources driving the V
matched otherwise the two inputs will have different set-
tling times, resulting in errors.
V IN+
ADC TRANSFER FUNCTION
The output coding for the AD7450 is two’s complement.
The designed code transitions occur at successive LSB
values (i.e. 1LSB, 2LSBs, etc.) and the LSB size is
2xV
AD7450 is shown in figure 5.
V IN-
V IN-
REF
/4096. The ideal transfer characteristic of the
Figure 4. ADC Conversion Phase
Figure 3. ADC Acquisition Phase
A
B
B
A
B
A
A
B
SW1
SW2
SW1
SW2
V REF
V REF
IN+
and the V
C s
C s
C s
C s
The Control Logic generates the
SW3
SW3
IN-
pins must be
COMPARATOR
COMPARATOR
The Control
AD7450
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
CONTROL
LOGIC
CONTROL
LOGIC
DAC
DAC
DAC
DAC