EVAL-CONTROLBRD2 AD [Analog Devices], EVAL-CONTROLBRD2 Datasheet - Page 18

• Manufacturer Part Number: EVAL-CONTROLBRD2
• Description: Differential Input, 1MSPS, 12-Bit ADC in ?SO-8 and S0-8
• Manufacturer: AD [Analog Devices]

SCLK
This 664ns satisfies the requirement of 275ns for t
From Figure 20, t
where t
satisfying the minimum requirement of 100ns.
As in this example and with other slower clock values, the
signal may already be acquired before the conversion is
complete but it is still necessary to leave 100ns minimum
t
be fully acquired at approximately point C in Figure 20.
MODES OF OPERATION
The mode of operation of the AD7450 is selected by
controlling the logic state of the
conversion.
Normal Mode and Power-Down Mode. The point at which
determine whether or not the AD7450 will enter the power-
down mode.
controls whether the device will return to normal operation
or remain in power-down.
designed to provide flexible power management options.
These options can be chosen to optimize the power dissipa-
tion/throughput rate ratio for differing application
requirements.
Normal Mode
This mode is intended for fastest throughput rate perfor-
mance. The user does not have to worry about any
power-up times as the AD7450 is kept fully powered up.
Figure 21 shows the general diagram of the operation of
the AD7450 in this mode. The conversion is initiated on
the falling edge of
Section’. To ensure the part remains fully powered up,
have elapsed after the falling edge of
If
ing edge, but before the 16th SCLK falling edge, the part
will remain powered up but the conversion will be termi-
nated and SDATA will go back into three-state.
AD7450
QUIET
2.5(1/F
is pulled high after the conversion has been initiated will
must remain low until at least 10 SCLK falling edges
between conversions. In example 2 the signal should
is brought high any time after the 10th SCLK fall-
8
10ns
= 45ns. This allows a value of 119ns for t
SCLK
t 2
There are two possible modes of operation,
) + t
Similarly, if already in power-down,
1
8
ACQ
+ t
as described in the ‘Serial Interface
QUIET
comprises of:
2
PRELIMINARY TECHNICAL DATA
These modes of operation are
3
12.5(1/f SCLK )
Figure 20. Serial Interface Timing example
.
4
signal during a
t 5
t
CONVERT
ACQ
5
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1/Throughput
.
–18–
SDATA
state enabled will never be greater than t
Sixteen serial clock cycles are required to complete the
conversion and access the complete conversion result.
may idle high until the next conversion or may idle low
until sometime prior to the next conversion. Once a data
transfer is complete, i.e. when SDATA has returned to
three-state, another conversion can be initiated after the
quiet time, t
Power Down Mode
This mode is intended for use in applications where
slower throughput rates are required; either the ADC is
powered down between each conversion, or a series of
conversions may be performed at a high throughput rate
and the ADC is then powered down for a relatively long
duration between these bursts of several conversions.
When the AD7450 is in the power down mode, all analog
circuitry is powered down. To enter power down mode,
the conversion process must be interrupted by bringing
and before the tenth falling edge of SCLK as shown in
Figure 22.
Once
SCLKs, the part will enter power down and the conver-
sion that was initiated by the falling edge of
terminated and SDATA will go back into three-state.
The time from the rising edge of
‘Timing Specifications’).
the second SCLK falling edge, the part will remain in
normal mode and will not power-down.
accidental power-down due to glitches on the
SCLK
high anywhere after the second falling edge of SCLK
13
B
has been brought high in this window of
Figure 21. Normal Mode Operation
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1
14
t 6
4 LEADING ZEROS + CONVERSION RESULT
has elapsed by again bringing
C
15
If
t 8
16
t ACQUISITION
is brought high before
10
to SDATA three-
8
This will avoid
t
(see the
QUIET
will be
REV. PrJ
line.
16
low.