EVAL-CONTROLBRD2 AD [Analog Devices], EVAL-CONTROLBRD2 Datasheet - Page 17

• Manufacturer Part Number: EVAL-CONTROLBRD2
• Description: Differential Input, 1MSPS, 12-Bit ADC in ?SO-8 and S0-8
• Manufacturer: AD [Analog Devices]

SERIAL INTERFACE
Figure 19 shows a detailed timing diagram for the serial
interface of the AD7450.
conversion clock and also controls the transfer of data
from the AD7450 during conversion.
conversion process and frames the data transfer. The fall-
ing edge of
and takes the bus out of three-state. The analog input is
sampled and the conversion initiated at this point. The
conversion will require 16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track and
hold will go back into track on the next SCLK rising edge
as shown at point B in Figure 19. On the 16th SCLK
falling edge the SDATA line will go back into three-state.
If the rising edge of
elapsed, the conversion will be terminated and the SDATA
line will go back into three-state on the 16th SCLK falling
edge. 16 serial clock cycles are required to perform a
conversion and to access data from the AD7450.
low provides the first leading zero to be read in by the micro-
controller or DSP. The remaining data is then clocked out
on the subsequent SCLK falling edges beginning with the
second leading zero. Thus the first falling clock edge on the
serial clock provides the second leading zero. The final bit
in the data transfer is valid on the 16th falling edge, having
been clocked out on the previous (15th) falling edge.
REV. PrJ
SDATA
SCLK
+2.5V
Figure 18. Applying a Bipolar Single Ended Input to the
-2.5V
0V
t 2
puts the track and hold into hold mode
0
V IN
4 LEADING ZERO’S
1
t 3
0
R
R
R
occurs before 16 SCLKs have
AD7450
EXTERNAL
V REF (2.5V)
The serial clock provides the
2
PRELIMINARY TECHNICAL DATA
R
0
0.1µF
3
+2.5V
+ 5V
0V
0
Figure 19. Serial interface Timing Diagram
initiates the
4
t 4
V IN+
V IN-
DB11
t 5
AD7450
t
CONVE RT
5
V REF
DB10
going
t 7
–17–
In applications with a slower SCLK, it may be possible to
read in data on each SCLK rising edge i.e. the first rising
edge of SCLK after the
leading zero provided and the 15th SCLK edge would have
DB0 provided.
Timing Example 1
Having F
1MSPS gives a cycle time of:
A cycle consists of:
Therefore if t
This 296ns satisfies the requirement of 275ns for t
From Figure 20, t
where t
satisfying the minimum requirement of 100ns.
Timing Example 2
Having F
315kSPS gives a cycle time of :
A cycle consists of:
Therefore if t
t
ACQ
1/Throughput = 1/1000000 = 1µs
t
10ns + 12.5(1/18MHz) + t
t
2.5(1/F
10ns + 12.5(1/5MHz) + t
1/Throughput = 1/315000 = 3.174µs
t
2
ACQ
2
1 3
+ 12.5 (1/F
+ 12.5 (1/F
= 664ns
B
DB2
8
= 296ns
SCLK
= 45ns. This allows a value of 113ns for t
SCLK
SCLK
14
t 6
) + t
2
2
= 18MHz and a throughput rate of
= 5MHz and a throughput rate of
= 10ns then:
DB1
is 10ns then:
SCLK
SCLK
ACQ
8
15
) + t
+ t
) + t
comprises of:
DB0
QUIET
t 8
ACQ
ACQ
16
ACQ
ACQ
= 3.174µs.
= 1µs.
falling edge would have the
3 -STATE
= 3.174µs
= 1µs
t QUIET
t 1
AD7450
ACQ
QUIET
.