EVAL-ADV7320EB AD [Analog Devices], EVAL-ADV7320EB Datasheet - Page 69

• Manufacturer Part Number: EVAL-ADV7320EB
• Description: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
• Manufacturer: AD [Analog Devices]

APPENDIX 3—SD CLOSED CAPTIONING
[Subaddresses 0x51 to 0x54]
The ADV7320/ADV7321 support closed captioning conforming
to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of the even fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by Logic 1 start bit. Sixteen bits of data follow the start
bit. These consist of two 8-bit bytes, seven data bits, and one
odd parity bit. The data for these bytes is stored in the SD
closed captioning registers [Addresses 0x53 to 0x54].
The ADV7320/ADV7321 also support the extended closed
captioning operation, which is active during even fields and
encoded on Scan Line 284. The data for this operation is stored
in the SD closed captioning registers [Addresses 0x51 to 0x52].
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the
ADV7320/ ADV7321. All pixels inputs are ignored during
Lines 21 and 284 if closed captioning is enabled.
50 IRE
40 IRE
FREQUENCY = F
REFERENCE COLOR BURST
AMPLITUDE = 40 IRE
10.5 ± 0.25µs
10.003µs
(9 CYCLES)
SC
= 3.579545MHz
Figure 98. Closed Captioning Waveform, NTSC
27.382µs
Rev. 0 | Page 69 of 88
CLOCK RUN-IN
7 CYCLES OF
0.5035MHz
12.91µs
FCC Code of Federal Regulations (CFR) 47 section 15.119 and
EIA608 describe the closed captioning information for Line 21
and Line 284.
The ADV7320/ADV7321 use a single buffering method. This
means that the closed captioning buffer is only 1 byte deep;
therefore, there will be no frame delay in outputting the closed
captioning data, unlike other 2-byte-deep buffering systems.
The data must be loaded one line before it is output on Line 21
and Line 284. A typical implementation of this method is to use
VSYNC to interrupt a microprocessor, which in turn will load
the new data (2 bytes) in every field. If no new data is required
for transmission, 0s must be inserted in both data registers; this
is called nulling. It is also important to load control codes, all of
which are double bytes, on Line 21, or a TV will not recognize
them. If there is a message such as “Hello World” that has an
odd number of characters, it is important to add a blank
character at the end so that the end-of-caption, 2-byte control
code lands in the same field.
A
R
S
T
T
D0–D6
TWO 7-BIT + PARITY
ASCII CHARACTERS
BYTE 0
33.764µ s
(DATA)
A
R
P
T
Y
I
D0–D6
BYTE 1
A
R
P
T
Y
I
ADV7320/ADV7321