EVAL-ADV7320EB AD [Analog Devices], EVAL-ADV7320EB Datasheet - Page 34

• Manufacturer Part Number: EVAL-ADV7320EB
• Description: Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
• Manufacturer: AD [Analog Devices]

ADV7320/ADV7321
Table 17. Registers 0x4A to 0x58
SR7–
SR0
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
1
For precise NTSC Fsc, this register should be programmed to 0x1F.
Register
SD Timing
Register 0
SD Timing
Register 1
SD F
SD F
SD F
SD F
SD F
SD Closed
Captioning
SD Closed
Captioning
SD Closed
Captioning
SD Closed
Captioning
SD Pedestal
Register 0
SD Pedestal
Register 1
SD Pedestal
Register 2
SD Pedestal
Register 3
SC
SC
SC
SC
SC
Register 0
Register 1
Register 2
Register 3
Phase
1
Bit Description
SD Slave/Master
Mode
SD Timing Mode
SD BLANK Input
SD Luma Delay
SD Min. Luma
Value
SD Timing Reset
SD HSYNC Width
SD HSYNC to
VSYNC Delay
SD HSYNC to VSYNC
Rising Edge Delay
(Mode 1 Only)
VSYNC Width
(Mode 2 Only)
HSYNC to Pixel
Data Adjust
Extended Data on
Even Fields
Extended Data on
Even Fields
Data on Odd Fields
Data on Odd Fields
Pedestal on Odd
Fields
Pedestal on Odd
Fields
Pedestal on Even
Fields
Pedestal on Even
Fields
HSYNC
VSYNC
t
LINE 1
B
Bit 7
x
0
0
1
1
x
x
x
x
x
x
x
x
x
17
25
17
25
t
A
Bit 6
0
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
16
24
16
24
Figure 48. Timing Register 1 in PAL Mode
Bit 5
0
0
1
1
0
x
x
0
0
1
1
x
x
x
x
x
x
x
x
x
15
23
15
23
Rev. 0 | Page 34 of 88
Bit 4
0
1
0
1
0
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
14
22
14
22
Bit 3
0
1
0
0
0
1
1
x
x
x
x
x
x
x
x
x
13
21
13
21
Bit 2
0
0
1
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
12
20
12
20
t
C
LINE 313
Bit 1
0
1
0
1
0
0
0
1
1
x
x
x
x
x
x
x
x
x
11
19
11
19
0
1
0
0
1
0
1
x
x
x
x
x
x
x
x
x
18
10
18
Bit 0
10
LINE 314
Register Setting
Slave mode.
Master mode.
Mode 0.
Mode 1.
Mode 2.
Mode 3.
Enabled.
Disabled.
No delay.
2 clk cycles.
4 clk cycles.
6 clk cycles.
−40 IRE.
−7.5 IRE.
A low-high-low transition will
reset the internal SD timing
counters.
T
T
T
T
T
T
T
T
T
T
1 clk cycle.
4 clk cycles.
16 clk cycles.
128 clk cycles.
0 clk cycles.
1 clk cycle.
2 clk cycles.
3 clk cycles.
Subcarrier Frequency Bits 7 to 0.
Subcarrier Frequency Bits 15 to 8.
Subcarrier Frequency Bits 23 to 16.
Subcarrier Frequency Bits 31 to 24.
Subcarrier Phase Bits 9 to 2.
Extended Data Bits 7 to 0.
Extended Data Bits 15 to 8.
Data Bits 7 to 0.
Data Bits 15 to 8.
Setting any of these bits to 1 will
disable pedestal on the line num-
ber indicated by the bit settings.
a
a
a
a
b
b
b
b
c
c
= T
= T
= 1 clk cycle.
= 4 clk cycles.
= 16 clk cycles.
= 128 clk cycles.
= 0 clk cycle.
= 4 clk cycles.
= 8 clk cycles.
= 18 clk cycles.
b
b
.
+ 32 µs.
Reset
Value
0x08
0x00
0x1E
0x7C
0xF0
0x21
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
1