EVAL-ADV7320EB AD [Analog Devices], EVAL-ADV7320EB Datasheet - Page 45
![no-image](/images/no-image-200.jpg)
EVAL-ADV7320EB
Manufacturer Part Number
EVAL-ADV7320EB
Description
Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
Manufacturer
AD [Analog Devices]
Datasheet
1.EVAL-ADV7320EB.pdf
(88 pages)
- Current page: 45 of 88
- Download datasheet (2Mb)
RESET SEQUENCE
A reset is activated with a high-to-low transition on the RESET
pin (Pin 33) according to the timing specifications, and the
ADV7320/ADV7321 reverts to the default output
configuration. Figure 63 illustrates the RESET timing sequence.
SD VCR FF/RW SYNC
[Subaddress 0x42, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for
nonstandard input video, i.e., in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields are reached; in rewind mode, this sync
DIGITAL TIMING
PIXEL DATA
RESET
A, B, C
VALID
DACs
XXXXXX
XXXXXX
DIGITAL TIMING SIGNALS SUPPRESSED
Figure 63. RESET Timing Sequence
Rev. 0 | Page 45 of 88
OFF
signal usually occurs after the total number of lines/fields are
reached. Conventionally this means that the output video will
have corrupted field signals, because one signal is generated by
the incoming video and another is generated when the internal
lines/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled [Subaddress 0x42,
Bit 5], the lines/fields counters are updated according to the
incoming VSYNC signal, and the analog output matches the
incoming VSYNC signal.
This control is available in all slave timing modes except Slave
Mode 0.
ADV7320/ADV7321
TIMING ACTIVE
VALID VIDEO
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