EVAL-ADAU1401EB AD [Analog Devices], EVAL-ADAU1401EB Datasheet - Page 25

• Manufacturer Part Number: EVAL-ADAU1401EB
• Description: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
• Manufacturer: AD [Analog Devices]

SPI PORT
By default, the ADAU1401 is in I
SPI control mode by pulling CLATCH/WP low three times. The
SPI port uses a 4-wire interface, consisting of CLATCH, CCLK,
CDATA, and COUT signals, and is always a slave port. The
CLATCH signal should go low at the beginning of a transaction
and high at the end of a transaction. The CCLK signal latches
CDATA during a low-to-high transition. COUT data is shifted
out of the ADAU1401 on the falling edge of CCLK and should be
clocked into a receiving device, such as a microcontroller, on the
CCLK rising edge. The CDATA signal carries the serial input
data, and the COUT signal is the serial output data. The COUT
signal remains three-stated until a read operation is requested.
This allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions have the same basic format
shown in
data should be written MSB first. The ADAU1401 cannot be
taken out of SPI mode without a full reset.
Chip Address R/ W
The first byte of an SPI transaction includes the 7-bit chip address
and a R/ W bit. The chip address is set by the ADDR0 pin. This
allows two ADAU1401s to share a CLATCH signal, yet still operate
independently. When ADDR0 is low, the chip address is 0000000;
when it is high, the address is 0000001 (see Table 18). The LSB
of this first byte determines whether the SPI transaction is a
read (Logic Level 1) or a write (Logic Level 0).
Table 19. Generic Control Word Format
Byte 0
chip_adr [6:0], R/W
1
Continues to end of data.
Table 19. A timing diagram is shown in Figure 4. All
CLATCH
CDATA
CCLK
CLATCH
CDATA
CCLK
COUT
2
C mode, but it can be put into
BYTE 0
Byte 1
0000, subadr [11:8]
HI-Z
Figure 27. SPI Read from ADAU1401 Clocking (Single-Read Mode)
BYTE 0
Figure 26. SPI Write to ADAU1401 Clocking (Single-Write Mode)
BYTE 1
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Byte 2
subadr [7:0]
DATA
Table 18. ADAU1401 SPI Address Byte Format
Bit 0
0
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register. The MSBs of the subaddress
are zero-padded to bring the word to a full 2-byte length.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. During a burst mode write, an initial
subaddress is written followed by a continuous sequence of data
for consecutive memory/register locations. The detailed data
format for continuous mode operation is shown in
Table 26 in the Read/Write Data Formats section.
A sample timing diagram for a single-write SPI operation to the
parameter RAM is shown in
of a single-read SPI operation is shown in Figure 27. The COUT
pin goes from three-state to being driven at the beginning of
Byte 3. In this example, Byte 0 to Byte 2 contain the addresses
and the R/
BYTE 1
Bit 1
0
W bit and subsequent bytes carry the data.
DATA
Bit 2
0
BYTE 2
Byte 3
data
Bit 3
0
Figure 26. A sample timing diagram
DATA
Bit 4
0
BYTE 3
HI-Z
Bit 5
0
Byte 4
data
ADAU1401
Bit 6
ADDR0
1
Table 24 and
Bit 7
R/W