EVAL-ADAU1401EB AD [Analog Devices], EVAL-ADAU1401EB Datasheet - Page 12

• Manufacturer Part Number: EVAL-ADAU1401EB
• Description: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
• Manufacturer: AD [Analog Devices]

ADAU1401
Pin No.
38
39
40
41
43
44
45
46
47
1
input/output.
PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D_IO/A_IO = digital input/output or analog
Mnemonic
PLL_MODE0
PLL_MODE1
CM
FILTD
VOUT3
VOUT2
VOUT1
VOUT0
FILTA
Type
D_IN
D_IN
A_OUT
A_OUT
A_OUT
A_OUT
A_OUT
A_OUT
A_OUT
1
Page No.
17
17
20
20
20
20
Rev. 0 | Page 12 of 52
Description
PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency
of the master clock PLL. See the Setting Master Clock/PLL Mode section for
more details.
1.5 V Common-Mode Reference. A 47 μF decoupling capacitor should be
connected between this pin and ground to reduce crosstalk between the ADCs
and DACs. The material of the capacitors is not critical. This pin can be used to
bias external analog circuits, as long as those circuits are not drawing current
from the pin (such as when CM is connected to the noninverting input of
an op amp).
DAC Filter Decoupling Pin. A 10 μF capacitor should be connected between
this pin and ground. The capacitor material is not critical. The voltage on
this pin is 1.5 V.
VOUT0 to VOUT3 are the DAC Outputs. The full-scale output voltage is
0.9 V
reconstruction filters.
ADC Filter Decoupling Pin. A 10 μF capacitor should be connected between
this pin and ground. The capacitor material is not critical. The voltage on
this pin is 1.5 V.
rms
. These outputs can be used with either active or passive output