EVAL-AD1934EB AD [Analog Devices], EVAL-AD1934EB Datasheet - Page 23

• Manufacturer Part Number: EVAL-AD1934EB
• Description: 8-Channel DAC with PLL, 192 kHz, 24 Bits
• Manufacturer: AD [Analog Devices]

AUXILIARY TDM PORT CONTROL REGISTERS
Table 23. Auxiliary TDM Control 0
Bit
1:0
4:2
6:5
7
Table 24.
Bit
0
1
2
3
5:4
6
7
ADDITIONAL MODES
The AD1934 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 19 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This configuration
is applicable when the AD1934 master clock is generated by the
PLL with the DLRCLK as the PLL reference frequency.
Auxiliary TDM Control
Value
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
0
1
Value
0
1
0
1
0
1
0
1
00
01
10
11
0
1
0
1
Function
50/50 (allows 32/24/20/16 BCLK/channel)
Pulse (32 BCLK/channel)
Drive out on falling edge (DEF)
Drive out on rising edge
Left low
Left high
Slave
Master
64
128
256
512
Slave
Master
AUXTDMBCLK pin
Internally generated
Function
24
20
Reserved
16
1
0
8
12
16
Reserved
Reserved
Reserved
Reserved
Reserved
DAC aux mode
Reserved
Latch in midcycle (normal)
Latch in at end of cycle (pipeline)
1
Rev. 0 | Page 23 of 28
To relax the requirement for the setup time of the AD1934 in
cases of high speed TDM data transmission, the AD1934 can
latch in the data using the falling edge of DBCLK. This
effectively dedicates the entire BCLK period to the setup time.
This mode is useful in cases where the source has a large delay
time in the serial data driver. Figure 20 shows this pipeline
mode of data transmission.
Both the BLCK-less and pipeline modes are available.
Description
Word width
SDATA delay (BCLK periods)
Serial format
BCLK active edge (TDM in)
Description
LRCLK format
BCLK polarity
LRCLK polarity
LRCLK master/slave
BCLKs per frame
BCLK master/slave
BCLK source
AD1934