EVAL-AD1934EB AD [Analog Devices], EVAL-AD1934EB Datasheet
EVAL-AD1934EB
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EVAL-AD1934EB Summary of contents
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FEATURES PLL generated or direct master clock Low EMI design 108 dB DAC dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 ...
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AD1934 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Test Conditions............................................................................. 3 Analog Performance Specifications ........................................... 3 Crystal Oscillator Specifications................................................. 4 Digital Input/Output Specifications........................................... 4 ...
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SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply Voltages (AVDD, DVDD) 3 Temperature Range As specified in Table 1 and Table 2 Master Clock 12.288 ...
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AD1934 Specifications measured at 130°C (case). Table 2. Parameter DIGITAL-TO-ANALOG CONVERTERS Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) With A-Weighted Filter (Average) Total Harmonic Distortion + Noise Single-Ended Version Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset ...
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POWER SUPPLY SPECIFICATIONS Table 5. Parameter SUPPLIES Voltage Digital Current Normal Operation Power-Down Analog Current Normal Operation Power-Down DISSIPATION Operation All Supplies Digital Supply Analog Supply Power-Down, All Supplies POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins Conditions/Comments Min ...
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AD1934 DIGITAL FILTERS Table 6. Parameter DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay TIMING SPECIFICATIONS −40°C < T < +130°C, DVDD = 3.3 V ± 10%. A Table 7. Parameter INPUT MASTER ...
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Parameter DAC SERIAL PORT t DBH t DBL t DLS t DLH t DLS t DDS t DDH AUXTDM SERIAL PORT t ABH t ABL t ALS t ALH t ALS t DDS t DDH AUXILIARY INTERFACE t DXDD t ...
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AD1934 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under Absolute Maximum ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND MCLKI/XI MCLKO/XO AGND AVDD OR3 OR4 PD/RST DSDATA4 DGND CONNECT Table 10. Pin Function Description Pin No. In/Out Mnemonic 1 I AGND 2 I MCLKI/ MCLKO/ AGND ...
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AD1934 Pin No. In/Out Mnemonic 26 I CCLK/SCL 27 I CLATCH/ADR1 28 O OL1 29 O OR1 30 O OL2 31 O OR2 32 I AGND 33 I AVDD 34 I AGND 35 O FILTR 36 I AGND 37 I ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.06 0.04 0.02 0 –0.02 –0.04 –0. FREQUENCY (kHz) Figure 3. DAC Pass-Band Filter Response, 48 kHz 0 –50 –100 –150 FREQUENCY (kHz) Figure 4. DAC Stop-Band Filter Response, 48 kHz 0.10 ...
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AD1934 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTERS (DACs) The AD1934 DAC channels are arranged as single-ended, four stereo pairs giving eight analog outputs for minimum external components. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation and linear ...
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SERIAL CONTROL PORT The AD1934 has an SPI control port that permits programming and reading back of the internal control registers for the DACs and clock system. There is also a standalone mode available for operation without serial control that ...
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AD1934 POWER SUPPLY AND VOLTAGE REFERENCE The AD1934 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to ...
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Table 12. Pin Function Changes in TDM and AUX Modes Pin Name Stereo Modes AUXDATA1 Not Used (Float) DSDATA1 DAC1 Data In DSDATA2 DAC2 Data In DSDATA3 DAC3 Data In DSDATA4 DAC4 Data In AUXTDMLRCLK Not Used (Ground) AUXTDMBCLK Not ...
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AD1934 DAISY-CHAIN MODE The AD1934 also allows a daisy-chain configuration to expand the system 16 DACs (see Figure 12). In this mode, the DBCLK frequency is 512 f . The first eight slots of the DAC TDM data S stream ...
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DLRCLK DBCLK DSDATA1 DAC L1 DSDATA2 DAC L3 32 BITS MSB Figure 14. Dual-Line, DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode) LEFT CHANNEL LRCLK BCLK SDATA MSB LEFT CHANNEL LRCLK BCLK SDATA MSB LEFT CHANNEL LRCLK ...
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AD1934 t DBH DBCLK t DBL t DLS DLRCLK t DDS DSDATA LEFT-JUSTIFIED MSB MODE t DDH DSDATA 2 I S-JUSTIFIED MODE DSDATA RIGHT-JUSTIFIED MODE t ABH AUXTDMBCLK t ABL t ALS AUXTDMLRCLK DSDATA1 LEFT-JUSTIFIED MSB MODE DSDATA1 2 I ...
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Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12) Pin Name Stereo Modes AUXDATA1 Not Used (Float) DSDATA1 DAC1 Data In DSDATA2 DAC2 Data In DSDATA3 DAC3 Data In DSDATA4 DAC4 Data In AUXTDMLRCLK Not ...
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AD1934 CONTROL REGISTERS DEFINITIONS 2 C and SPI ports. The global address for the AD1934 is 0x04, shifted left 1 bit due to the R/ W bit. However, in The format is the same for ADR0 ...
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Table 17. PLL and Clock Control 1 Bit Value Function 0 0 PLL clock 1 MCLK 1 0 PLL clock 1 MCLK 2 0 Enabled 1 Disabled 3 0 Not locked 1 Locked 7:4 0000 Reserved DAC CONTROL REGISTERS Table ...
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AD1934 Table 20. DAC Control 2 Bit Value Function 0 0 Unmute 1 Mute 2:1 00 Flat 01 48 kHz curve 10 44.1 kHz curve 11 32 kHz curve 4 Reserved ...
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AUXILIARY TDM PORT CONTROL REGISTERS Table 23. Auxiliary TDM Control 0 Bit Value Function 1 Reserved 11 16 4:2 000 1 001 0 010 8 011 12 100 16 101 Reserved 110 Reserved 111 Reserved ...
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AD1934 DLRCLK INTERNAL DBCLK DSDATA DLRCLK INTERNAL DBCLK TDM-DSDATA Figure 19. Serial DAC Data Transmission in TDM Format Without DBCLK (Applicable Only If PLL Locks to DLRCLK) DLRCLK DBCLK MSB DSDATA 2 Figure 20 Pipeline Mode in DAC ...
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APPLICATION CIRCUITS Typical applications circuits are shown in Figure 21, Figure 22, and Figure 23. Recommended loop filters for LR clock and master clock as the PLL reference are shown in Figure 21. Output filters for the DAC outputs are ...
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... AD1934 OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 0.05 VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD1934YSTZ –40°C to +105°C 1 AD1934YSTZ-RL –40°C to +105°C EVAL-AD1934EB Pb-free part. 0.75 1.60 0.60 MAX 0.45 0.20 0.09 7° 3.5° 12 0° SEATING 0.08 MAX PLANE VIEW A 0.50 COPLANARITY BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 24 ...
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NOTES Rev Page AD1934 ...
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AD1934 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06106-0-6/07(0) Rev Page ...