EVAL-AD1934EB AD [Analog Devices], EVAL-AD1934EB Datasheet - Page 14

• Manufacturer Part Number: EVAL-AD1934EB
• Description: 8-Channel DAC with PLL, 192 kHz, 24 Bits
• Manufacturer: AD [Analog Devices]

AD1934
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1934 is designed for 3.3 V supplies. Separate power
supply pins are provided for the analog and digital sections.
These pins should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize noise
pickup. A bulk aluminum electrolytic capacitor of at least 22 μF
should also be provided on the same PC board as the codec. For
critical applications, improved performance is obtained with
separate supplies for the analog and digital sections. If this is
not possible, it is recommended that the analog and digital
supplies be isolated by means of a ferrite bead in series with
each supply. It is important that the analog supply be as
clean as possible.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
The DAC internal voltage reference (VREF) is brought out on
FILTR and should be bypassed as close as possible to the chip,
with a parallel combination of 10 μF and 100 nF. Any external
current drawn should be limited to less than 50 μA.
The internal reference can be disabled in PLL and Clock
Control 1 Register and FILTR can be driven from an external
source. This can be used to scale the DAC output to the clipping
level of a power amplifier based on its power supply voltage.
The CM pin is the internal common-mode reference. It should
be bypassed as close as possible to the chip, with a parallel
combination of 47 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the input
and output signal pins. The output current should be limited to
less than 0.5 mA source and 2 mA sink.
SERIAL DATA PORTS—DATA FORMAT
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The clock signals are all synchronous with the sample
rate. The normal stereo serial modes are shown in Figure 15.
The DAC serial data modes default to I
programmed for left-justified, right-justified, and TDM modes.
The word width is 24 bits by default and can be programmed
for 16 or 20 bits. The DAC serial formats are programmable
according to DAC Control 0 Register. The polarity of the
DBCLK and DLRCLK is programmable according to DAC
Control 1 Register. The auxiliary TDM port is also provided for
applications requiring more than eight DAC channels. In this
2
S. The ports can also be
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LRCLK
mode, the AUXTDMLRCLK and AUXTDMBCLK pins are
configured as TDM port clocks. In regular TDM mode, the
DLRCLK and DBCLK pins are used as the TDM port clocks.
The auxiliary TDM serial port’s format and its serial clock
polarity is programmable according to the Auxiliary TDM Port
Control 0 Register and Control 1 Register. Both DAC and
auxiliary TDM serial ports are programmable to become the
bus masters according to DAC Control 1 Register and auxiliary
TDM Control 1 Register. By default, both auxiliary TDM and
DAC serial ports are in the slave mode.
TIME-DIVISION MULTIPLEXED (TDM) MODES
The AD1934 serial ports also have several different TDM serial
data modes. The most commonly used configuration is shown
in Figure 10. In Figure 10, the eight on-chip DAC data slots are
packed into one TDM stream. In this mode, DBCLK is 256 f
The I/O pins of the serial ports are defined according to the
serial mode selected. For a detailed description of the function
of each pin in TDM and AUX Modes, see Table 12.
The AD1934 allows systems with more than eight DAC channels
to be easily configured by the use of an auxiliary serial data port.
The DAC TDM-AUX mode is shown in Figure 11. In this mode,
the AUX channels are the last four slots of the 16-channel TDM
data stream. These slots are extracted and output to the AUX
serial port. One major difference between the TDM mode and
an auxiliary TDM mode is the assignment of the TDM port
pins, as shown in Table 12. In auxiliary TDM mode, DBCLK
and DLRCLK are assigned as the auxiliary port clocks, and
AUXTDMBCLK and AUXTDMLRCLK are assigned as the
TDM port clocks. In regular TDM or 16-channel, daisy-chain
TDM mode, the DLRCLK and DBCLK pins are set as the TDM
port clocks. It should be noted that due to the high
AUXTDMBCLK frequency, 16-channel auxiliary TDM mode is
available only in the 48 kHz/44.1 kHz/32 kHz sample rate.
BCLK
DATA
32 BCLK
SLOT 1
LEFT 1
RIGHT 1
SLOT 2
Figure 10. DAC TDM (8-Channel I
MSB
SLOT 3
LEFT 2
MSB–1
RIGHT 2
SLOT 4
256 BCLKs
MSB–2
SLOT 5
LEFT 3
LRCLK
BCLK
DATA
RIGHT 3
SLOT 6
2
S Mode
SLOT 7
LEFT 4
RIGHT 4
SLOT 8
S
.