GS8162Z18B GSI [GSI Technology], GS8162Z18B Datasheet - Page 3
GS8162Z18B
Manufacturer Part Number
GS8162Z18B
Description
18Mb Pipelined and Flow Through Synchronous NBT SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS8162Z18B.pdf
(38 pages)
- Current page: 3 of 38
- Download datasheet (2Mb)
GS8162Z72 BGA Pin Description
Rev: 2.21 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
B
A
, B
B
Symbol
, B
A
B
E
V
MCH
DQ
MCL
ADV
TMS
TDO
DQ
DQ
DQ
DQ
DQ
DQ
DQ
LBO
TCK
V
TDI
V
0
G
NC
CK
PE
ZQ
An
C
1,
ZZ
E
FT
DDQ
W
G
, A
DD
,B
SS
,B
2
E
A
B
C
D
E
G
H
F
D,
H
3
1
B
E
, B
F
,
Type
I/O
—
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode)
3/38
Address field LSBs and Address Counter Preset Inputs
Burst Address Counter Advance Enable; active high
Byte Write Enable for DQ
Write Enable. Writes all enabled bytes; active low
Flow Through or Pipeline mode; active low
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
FLXDrive Output Impedance Control
Linear Burst Order mode; active low
Sleep Mode control; active high
DQ
Clock Input Signal; active high
Data Input and Output pins
Output driver power supply
Output Enable; active low
F
Chip Enable; active high
Chip Enable; active low
Scan Test Mode Select
, DQ
I/O and Core Ground
Scan Test Data Out
Must Connect High
Must Connect Low
Core power supply
Scan Test Data In
Scan Test Clock
Address Inputs
Description
G
No Connect
, DQ
H
A
I/Os; active low
, DQ
B
, DQ
C
, DQ
D,
DQ
E
,
© 1999, GSI Technology
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