GS8162Z18B GSI [GSI Technology], GS8162Z18B Datasheet - Page 12

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GS8162Z18B

Manufacturer Part Number
GS8162Z18B
Description
18Mb Pipelined and Flow Through Synchronous NBT SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
Rev: 2.21 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Key
Current State (n)
Clock (CK)
Command
Intermediate
ƒ
Current State and Next State Definition for
Transition
Input Command Code
Intermediate State (N+1)
High Z
(Data In)
B W
Current State
n
D
R
Pipeline Mode Data I/O State Diagram
Transition
ƒ
Intermediate
Next State (n+2)
12/38
n+1
B
Intermediate
Intermediate
Intermediate
D
W
State
High Z
GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)
ƒ
R
Pipeline Mode Data I/O State Diagram
Intermediate
Notes
1. The Hold command (CKE Low) is not
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
shown because it prevents any state change.
n+2
Next State
W
ƒ
D
Data Out
(Q Valid)
R
n+3
B
Intermediate
ƒ
© 1999, GSI Technology

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