GS8162Z18B GSI [GSI Technology], GS8162Z18B Datasheet

GS8162Z18B

Manufacturer Part Number

GS8162Z18B

Description

18Mb Pipelined and Flow Through Synchronous NBT SRAM

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS8162Z18B.pdf (38 pages)

Current page: 1 of 38
Download datasheet (2Mb)

119, 165, & 209 BGA

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• User-configurable Pipeline and Flow Through mode

• ZQ mode pin for user-selectable high/low output drive

• IEEE 1149.1 JTAG-compatible Boundary Scan

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 119-, 165-, or 209-Bump BGA package

Functional Description

The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit

Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT,

NtRAM, NoBL or other pipelined read/double late write or

flow through read/single late write SRAMs, allow utilization

of all available bus bandwidth by eliminating the need to insert

deselect cycles when the device is switched from read to write

cycles.

Rev: 2.21 11/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Read-Write-Read bus utilization; fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

Through

Pipeline

3-1-1-1

2-1-1-1

3.3 V

2.5 V

Flow

3.3 V

2.5 V

18Mb Pipelined and Flow Through

Synchronous NBT SRAM

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

Curr (x18)

Curr (x36)

Curr (x72)

tCycle

Parameter Synopsis

1/38

-250 -225 -200 -166 -150 -133 Unit

280

330

275

320

175

200

175

200

2.5

4.0

n/a

5.5

n/a

255

300

250

295

165

190

165

190

2.7

4.4

n/a

6.0

n/a

GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C)

Because it is a synchronous device, address, data inputs, and

read/write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by

the user to operate in Pipeline or Flow Through mode.

Operating as a pipelined synchronous device, in addition to the

rising-edge-triggered registers that capture input signals, the

device incorporates a rising edge triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge-triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with

GSI's high performance CMOS technology and is available in

a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 &

x36), or 209-bump (x72) BGA package.

230

270

350

230

265

335

160

180

225

160

180

225

3.0

5.0

6.5

200

230

300

195

225

290

150

170

150

170

115

3.4

6.0

7.0

185

215

270

180

210

260

145

165

210

145

165

210

3.8

6.7

7.5

165

190

245

165

185

235

135

150

185

135

150

185

4.0

7.5

8.5

250 MHz–133 MHz 2.5

2.5 V or 3.3 V I/O

V or 3.3 V V

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