LA-ISPMACH4000V LATTICE [Lattice Semiconductor], LA-ISPMACH4000V Datasheet - Page 4
LA-ISPMACH4000V
Manufacturer Part Number
LA-ISPMACH4000V
Description
3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
1.LA-ISPMACH4000V.pdf
(42 pages)
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Lattice Semiconductor
Figure 3. AND Array
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the LA-ispMACH 4000V/Z automotive family is 4+1 (total
5) product terms. The software automatically considers the availability and distribution of product term clusters as it
fits the functions within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path,
20-PT Speed Locking path and an up to 80-PT path. The availability of these three paths lets designers trade tim-
ing variability for increased performance.
The enhanced Logic Allocator of the LA-ispMACH 4000V/Z automotive family consists of the following blocks:
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Individual Product
Term Allocator
Cluster
In[34]
In[35]
In[0]
n
Note:
Indicates programmable fuse.
n+1
to
n-1
to
LA-ispMACH 4000V/Z Automotive Family Data Sheet
n-2
to
Allocator
Cluster
4
5-PT
from
n+2
from
n-1
from
from
n+1
n-4
PT0
PT1
PT2
PT3
PT4
PT75
PT76
PT77
PT78
PT79
From
n-4
PT80
PT81
PT82
Cluster 0
Cluster 15
Shared PT Clock
Shared PT Initialization
Shared PTOE
Steering Logic
SuperWIDE™
1-80
PTs
To n+4
To XOR (MC)
Fast 5-PT
Path
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