LA-ISPMACH4000V LATTICE [Lattice Semiconductor], LA-ISPMACH4000V Datasheet - Page 20

• Manufacturer Part Number: LA-ISPMACH4000V
• Description: 3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Timing Model
The task of determining the timing through the LA-ispMACH 4000V/Z automotive family, like any CPLD, is relatively
simple. The timing model provided in Figure 11 shows the specific delay paths. Once the implementation of a given
function is determined either conceptually or from the software report file, the delay path of the function can easily
be determined from the timing model. The Lattice design tools report the timing delays based on the same timing
model for a particular design. Note that the internal timing parameters are given for reference only, and are not
tested. The external timing parameters are tested and guaranteed for every device. For more information on the
timing model and usage, please refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage
Guidelines.
Figure 11. LA-ispMACH 4000V/Z Automotive Timing Model
SCLK
OE
Feedback
IN
From
t
Delays
t
GCLK_IN
In/Out
GOE
t
t
t
IOI
IOI
IN
t
IOI
t
t
INREG
INDIO
Control
t
Delays
ROUTE
t
BLA
t
t
PTCLK
t
t
PTSR
t
BCLK
LA-ispMACH 4000V/Z Automotive Family Data Sheet
BSR
MCELL
t
EXP
t
GPTOE
t
PTOE
20
Routing/GLB Delays
DATA
C.E.
S/R
t
t
PDb
MC Reg.
PDi
Q
Note: Italicized items are optional delay adders.
Register/Latch
Delays
t
ORP
Delays
In/Out
t
t
t
t
t
FBK
BUF
IOO
DIS
EN
Feedback
Out