LA-ISPMACH4000V LATTICE [Lattice Semiconductor], LA-ISPMACH4000V Datasheet
LA-ISPMACH4000V
Related parts for LA-ISPMACH4000V
LA-ISPMACH4000V Summary of contents
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... Lead-Free TQFP © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... The LA-ispMACH 4000V/Z automotive family has enhanced system integration capabilities. It supports 3.3V (4000V and 1.8V (4000Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The LA- ispMACH 4000V/Z also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing ...
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... GLB, they still must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associated I/O cells in the I/O block. ...
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... The software automatically considers the availability and distribution of product term clusters as it fits the functions within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed Locking path and 80-PT path. The availability of these three paths lets designers trade tim- ing variability for increased performance. ...
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... Product terms that used for control are steered either to the macrocell or I/O cell associated with the cluster. Table 3 shows the available functions for each of the five product terms in the cluster. The OR gate output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic allocator ...
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... Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable delay in this path allows designers to choose between the fastest possible set-up time and zero hold time. Figure 5. Macrocell ...
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... GLB Clock Generator Each LA-ispMACH 4000V/Z automotive device has up to four clock pins that are also routed to the GRP to be used as inputs. These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock signals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of com- binations of the true and complement edges of the global clock signals ...
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... OE product term to follow the macrocell output switched between I/O cells. Additionally, the out- put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the output routing multiplexers and feed the I/O cell directly. The enhanced ORP of the LA-ispMACH 4000V/Z family consists of the following elements: • ...
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... The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also allows the register output to bypass the ORP to achieve faster t Output Enable Routing Multiplexers The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell ...
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... Most LA-ispMACH 4000V/Z automotive family devices have a 4-bit wide Global OE Bus, except the LA-ispMACH 4032V and LA-ispMACH4032Z devices that have a 2-bit wide Global OE Bus. This bus is derived from a 4-bit inter- nal global OE PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be inverted ...
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... Zero Power/Low Power and Power Management The LA-ispMACH 4000V/Z automotive family is designed with high speed low power design techniques to offer both high speed and low power. With an advanced E CMOS logic approach), the LA-ispMACH 4000V/Z automotive family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low standby power without needing any “ ...
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... In-System Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, users get the ben- efi ...
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... Lattice Semiconductor and inputs without being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The LA-ispMACH 4000V/Z automotive devices provide this capability for input voltages in the range 0V to 3.0V. Density Migration The LA-ispMACH 4000V/Z automotive family has been designed to ensure that different density devices in the same package have the same pin-out ...
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... Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 2. Compliance with Lattice Thermal Management document is required. 3. All voltages referenced to GND. 4. Undershoot of -2V and overshoot Maximum of 64 I/Os per device with VIN > ...
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... Input or I/O leakage current is measured with the pin configured as an input I/O with the output driver tristated not measured with the output driver active. Bus maintenance circuits are disabled tolerant inputs and I/O should only be placed in banks where 3.0V ≤ 25° ...
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... Standby Power Supply Current LA-ispMACH 4064V Operating Power Supply Current ICC Standby Power Supply Current LA-ispMACH 4128V Operating Power Supply Current ICC Standby Power Supply Current LA-ispMACH 4000V/Z Automotive Family Data Sheet Over Recommended Operating Conditions Condition Vcc = 3.3V Vcc = 3.3V Vcc = 3.3V Vcc = 3.3V Vcc = 3.3V Vcc = 3.3V 16 Min ...
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... 3.6V bus maintenance turned off. V CCO IN CCO, 5. Includes V current without output loading. CCO LA-ispMACH 4000V/Z Automotive Family Data Sheet Over Recommended Operating Conditions Vcc = 1.8V, T Vcc = 1.9V, T Vcc = 1.9V, T Vcc = 1.9V, T Vcc = 1.8V, T Vcc = 1.9V, T Vcc = 1.9V, T Vcc = 1.9V, T Vcc = 1.8V, T Vcc = 1.9V, T Vcc = 1 ...
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... The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank. ...
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... Clock frequency with external feedback, [1/ (t MAX 1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards. 2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching. 3. Pulse widths and clock widths less than minimum will cause unknown behavior. ...
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... The Lattice design tools report the timing delays based on the same timing model for a particular design. Note that the internal timing parameters are given for reference only, and are not tested ...
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... CEH t Latch Setup Time (Global Clock Latch Setup Time (Product Term Clock) SL_PT t Latch Hold Time HL t Latch Gate to Output/Feedback MUX Time GOi t Propagation Delay through Transparent Latch to PDLi Output/Feedback MUX t Asynchronous Reset or Set to Output/Feedback SRi MUX Delay t Asynchronous Reset or Set Recovery Time ...
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... Global PT OE Delay GPTOE t Macrocell PT OE Delay PTOE Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. LA-ispMACH 4000V/Z Automotive Family Data Sheet Over Recommended Operating Conditions LA-ispMACH 4000V Description Min. 22 ...
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... BUF EN Note: Open drain timing is the same as corresponding LVCMOS timing. 1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders. LA-ispMACH 4000V/Z Automotive Family Data Sheet 1 LA-ispMACH 4000V Description Input register delay ...
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... BSCAN test Update reg, falling edge of clock to valid output BTUCO t BSCAN test Update reg, falling edge of clock to output disable BTUOZ t BSCAN test Update reg, falling edge of clock to output enable BTUOV LA-ispMACH 4000V/Z Automotive Family Data Sheet Parameter 24 Min. Max. Units 40 — ...
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... LA-ispMACH 4032V LA-ispMACH 4064V LA-ispMACH 4128V LA-ispMACH 4032Z LA-ispMACH 4064Z LA-ispMACH 4128Z 1. For further information about the use of these coefficients, refer to Technical Note TN1005, Power Estimation in ispMACH 4000V/B/C/Z Devices. LA-ispMACH 4000V/Z Automotive Family Data Sheet vs. Frequency CC 100 80 60 4128V 40 4064V ...
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... Figure 12. Output Test Load, LVTTL and LVCMOS Standards Table 9. Test Fixture Required Components Test Condition LVCMOS I/O, (L -> -> L) LVCMOS I/O (Z -> H) LVCMOS I/O (Z -> L) LVCMOS I/O (H -> Z) LVCMOS I/O (L -> includes test fixtures and probe capacitance. L LA-ispMACH 4000V/Z Automotive Family Data Sheet V CCO R 1 DUT ...
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... GND CLK0/I, CLK1/I, CLK2/I, CLK3 CCO0 CCO1 yzz 1. In some packages, certain I/Os are only available for use as inputs. See the signal connections table for details. LA-ispMACH 4000V ORP Reference Table 4032V 1 Number of I/Os 30 Number of GLBs 2 Number of I/Os /GLB 16 Reference ORP Table 16 I/Os / GLB 1 ...
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... Lattice Semiconductor LA-ispMACH 4000V/Z Power Supply and NC Connections 2 Signal 44 TQFP VCC 11, 33 VCCO0 6 VCCO (Bank 0) VCCO1 28 VCCO (Bank 1) GND 12, 34 GND (Bank 0) 5 GND (Bank None 1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with the bank shown ...
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... Lattice Semiconductor LA-ispMACH 4032V and 4064V Logic Signal Connections: 44-Pin TQFP Pin Number Bank Number ...
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... Lattice Semiconductor LA-ispMACH 4032V and 4064V Logic Signal Connections: 44-Pin TQFP Pin Number Bank Number LA-ispMACH 4032V/Z and 4064V/Z Logic Signal Connections: 48-Pin TQFP Pin Number Bank Number ...
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... Lattice Semiconductor LA-ispMACH 4032V/Z and 4064V/Z Logic Signal Connections: 48-Pin TQFP Pin Number Bank Number LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP Pin Number Bank Number ...
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... Lattice Semiconductor LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP Pin Number Bank Number 27 ...
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... Lattice Semiconductor LA-ispMACH 4064V/Z and 4128V/Z Logic Signal Connections: 100-Pin TQFP Pin Number Bank Number 73 77 ...
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... Lattice Semiconductor LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP Pin Number LA-ispMACH 4000V/Z Automotive Family Data Sheet Bank Number GLB/MC/Pad ...
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... Lattice Semiconductor LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP (Cont.) Pin Number LA-ispMACH 4000V/Z Automotive Family Data Sheet Bank Number ...
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... Lattice Semiconductor LA-ispMACH 4128V Logic Signal Connections: 128-Pin TQFP (Cont.) Pin Number 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 ...
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... Lattice Semiconductor LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP Pin Number LA-ispMACH 4000V/Z Automotive Family Data Sheet Bank Number GLB/MC/Pad ...
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... Lattice Semiconductor LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.) Pin Number LA-ispMACH 4000V/Z Automotive Family Data Sheet Bank Number ...
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... Lattice Semiconductor LA-ispMACH 4128V Logic Signal Connections: 144-Pin TQFP (Cont.) Pin Number 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 ...
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... For device migration considerations, these NC pins are GND pins for I/O banks in LA-ispMACH 4128V devices. LA-ispMACH 4000V/Z Automotive Family Data Sheet Bank Number GLB/MC/Pad - 0 A0/GOE0 VCCO (Bank 0) ...
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... Products are not designed, intended or warranted to be fail-safe and are not designed, intended or warranted for use in applications related to the deployment of airbags. Further, products are not intended to be used, designed or warranted for use in applications that affect the control of the vehicle unless there is a fail-safe or redundancy fea- ture and also a warning signal to the operator of the vehicle upon failure ...
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... Updated ispMACH 4000 Introduction section. Updated Signal Descriptions table. September 2007 02.2 DC Electrical Characteristics table, removed duplicate specifications. July 2008 02.3 Lowered the maximum supply current at 85°C to match the commercial product values. Added automotive disclaimer. LA-ispMACH 4000V/Z Automotive Family Data Sheet Change Summary 42 ...