GS8161FZ18BD GSI [GSI Technology], GS8161FZ18BD Datasheet - Page 5

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GS8161FZ18BD

Manufacturer Part Number
GS8161FZ18BD
Description
18Mb Flow Through Synchronous NBT SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
Rev: 1.00 6/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161FZ18/32/36BD 165-Bump BGA Pin Description
B
A
Symbol
, B
A
V
MCH
CKE
ADV
TMS
TDO
DQ
DQ
DQ
DQ
LBO
TCK
V
TDI
V
B
0
NC
CK
ZZ
E
E
E
DDQ
W
G
A
, B
, A
DD
SS
1
3
2
A
B
C
D
1
C
, B
D
Type
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
5/28
Address field LSBs and Address Counter Preset Inputs
Burst address counter advance enable; active high
Clock Input Buffer Enable; active low
Linear Burst Order mode; active low
Sleep mode control; active high
Clock Input Signal; active high
Data Input and Output pins
Output driver power supply
Output Enable; active low
Chip Enable; active high
Write Enable; active low
Chip Enable; active low
Chip Enable; active low
Scan Test Mode Select
I/O and Core Ground
Scan Test Data Out
Must Connect High
Core power supply
Scan Test Data In
Scan Test Clock
Address Inputs
Description
No Connect
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
GS8161FZ18/32/36BD
© 2006, GSI Technology

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