GS8161FZ18BD GSI [GSI Technology], GS8161FZ18BD Datasheet - Page 23

• Manufacturer Part Number: GS8161FZ18BD
• Description: 18Mb Flow Through Synchronous NBT SRAM
• Manufacturer: GSI [GSI Technology]

JTAG Port Recommended Operating Conditions and DC Characteristics (2.5/3.3 V Version)
JTAG Port AC Test Conditions
Notes:
1.
2.
Rev: 1.00 6/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Include scope and jig capacitance.
Test conditions as shown unless otherwise noted.
Input Under/overshoot voltage must be –2 V < Vi < V
V
0 V ≤ V
Output Disable, V
The TDO output driver is served by the V
I
I
I
I
OHJ
OLJ
OHJC
OLJC
ILJ
Output reference level
Input reference level
= + 4 mA
= –4 mA
≤ V
= –100 uA
= +100 uA
Input high level
Input slew rate
Input low level
Parameter
IN
IN
TMS, TCK and TDI Input Leakage Current
TMS, TCK and TDI Input Leakage Current
≤ V
≤ V
2.5 V Test Port Input High Voltage
2.5 V Test Port Input High Voltage
3.3 V Test Port Input High Voltage
3.3 V Test Port Input Low Voltage
ILJn
TDO Output Leakage Current
Test Port Output High Voltage
Test Port Output Low Voltage
DDn
Test Port Output CMOS High
Test Port Output CMOS Low
OUT
= 0 to V
Parameter
DDn
DDQ
Conditions
V
supply.
DD
V
V
1 V/ns
0.2 V
DDQ
DDQ
– 0.2 V
/2
/2
DDn
23/28
+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
Symbol
V
V
V
V
V
V
V
I
V
I
I
INHJ
OHJC
INLJ
OLJC
OLJ
IHJ2
IHJ2
IHJ3
ILJ3
OHJ
OLJ
V
DDQ
DQ
0.6 * V
0.6 * V
Min.
–300
–0.3
– 100 mV
2.0
1.7
–1
–1
—
—
DD2
DD2
* Distributed Test Jig Capacitance
JTAG Port AC Test Load
V
V
V
V
GS8161FZ18/32/36BD
100 mV
DD2
DD2
DD3
Max.
DDQ
100
0.8
0.4
—
—
1
1
+0.3
+0.3
+0.3
/2
50Ω
© 2006, GSI Technology
Unit Notes
uA
uA
uA
V
V
V
V
V
V
V
V
30pF
*
5, 6
5, 7
5, 8
5, 9
1
1
1
1
2
3
4