GS8161FZ18BD GSI [GSI Technology], GS8161FZ18BD Datasheet

GS8161FZ18BD

Manufacturer Part Number

GS8161FZ18BD

Description

18Mb Flow Through Synchronous NBT SRAM

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS8161FZ18BD.pdf (28 pages)

Current page: 1 of 28
Download datasheet (2Mb)

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

• Fully pin-compatible with flow through NtRAM™, NoBL™

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 2.5 V or 3.3 V +10%/–10% core power supply

• LBO pin for Linear or Interleave Burst mode

• Pin-compatible with 2M, 4M, and 8M devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ pin for automatic power-down

• JEDEC-standard 165-bump FP-BGA package

• RoHS-compliant 165-bump BGA package available

Functional Description

The GS8161FZ18/32/36BD is an 18Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other flow through read/single late write SRAMs, allow

utilization of all available bus bandwidth by eliminating the

need to insert deselect cycles when the device is switched from

read to write cycles.

Rev: 1.00 6/2006

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization

and ZBT™ SRAMs

Flow Through

2-1-1-1

Curr

Synchronous NBT SRAM

Curr

tCycle

Parameter Synopsis

(x32/x36)

18Mb Flow Through

(x18)

1/28

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable, ZZ and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8161FZ18/32/36BD is configured to operate in Flow

Through mode.

The GS8161FZ18/32/36BDis implemented with GSI's high

performance CMOS technology and is available in JEDEC-

standard 165-bump FP-BGA package.

-5.5

225

255

5.5

-6.5

200

220

6.5

-7.5

185

205

7.5

Unit

GS8161FZ18/32/36BD

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

5.5 ns–7.5 ns

Related parts for GS8161FZ18BD

Related keywords

GS8161FZ18BD datasheet
GS8161FZ18BD data sheet
GS8161FZ18BD pdf datasheet
GS8161FZ18BD component
GS8161FZ18BD part
GS8161FZ18BD distributor
GS8161FZ18BD RoHS
GS8161FZ18BD datasheet download