UPD64084 NEC, UPD64084 Datasheet - Page 61

• Manufacturer Part Number: UPD64084
• Description: THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
• Manufacturer: NEC

Clock and Timing Generation Section AC Characteristics
(DV
ADC and DAC Section AC Characteristics (AV
Note
I
(DV
T
2
Subcarrier output frequency
Subcarrier output amplitude
Clock output frequency
Clock output duty factor
f
Horizontal sync attenuation
(Capture range)
Vertical sync attenuation
(Capture range)
ADC acquisition time
DAC setting time
SDA pin ACK response delay
SDA data set-up time
SDA data hold time
SC
C Bus Interface Section AC Characteristics
A
= 0 to + 70°C)
DD
DD
pull-in range (in f
= 2.5 ± 0.2 V, DGND = 0 V, C
= DV
Excluding data conversion delay
Parameter
Parameter
Parameter
AYO, ACO
DDRAM
(from Master)
CLK8
Note
AYI
SC
= AV
Note
terms)
(Slave)
SDA
SCL
DD
= 2.5 ±0.2 V, DV
Hi-Z
f
V
f
D
f
V
V
t
t
t
t
t
FSCO
CLK8OUT
bp
ACKAD
SETDA
ACK
SU:DAT
HD:DAT
Symbol
Symbol
Symbol
FSCO
CLK8OUT
hi
vi
L
8th Clock
= 15 pF, T
FSCO pin
FSCO pin, AV
CLK8 pin, CKMD pin = DGND,
CLK8OFF (SA07:D4) = 0
When the burst locked clock operation
Sync input amplitude, HSSL = 1111,
VSSL = 1000
(assumed to be 0dB when inputting
40IRE = 59LSB)
CLK8
CLK8
SCL
SDA:L
SCL
DDIO
A
Data Sheet S16021EJ2V0DS
t
= 0 to +70 °C)
ACK
DD
= 3.3 ±0.3 V, DGND = DGNDRAM = AGND = 0 V, C
SDA
SDA:Hi-Z
t
= 2.5 ± 0.2 V, AGND = 0 V, C
ACKAD
SCL
AYI
AYO, ACO
t
SU:DAT
Conditions
Conditions
Conditions
DD
= 3.3 V
9th Clock
t
HD:DAT
t
SETDA
L
MIN.
MIN.
MIN.
100
45
= 15 pF, T
0
8
6
1st Clock
3.579545
28.63636
TYP.
TYP.
TYP.
1.00
A
50
600
15
0
0
7
= +25 °C)
MAX.
MAX.
MAX.
500
55
PD64084
L
= 15 pF,
MHz
MHz
Unit
Unit
Unit
V
Hz
dB
dB
ns
ns
ns
ns
ns
%
p-p
61