UPD64084 NEC, UPD64084 Datasheet - Page 35

• Manufacturer Part Number: UPD64084
• Description: THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
• Manufacturer: NEC

14.3.2
EXDAS (SA01h: D7)
N3D1STEN (SA01h: D5)
CLK20LOW (SA01h: D2)
ADCPMD (SA04h: D5, D4)
DIR3DYC (SA08h: D7, D6)
DCPAG (SA08h: D5 to D3)
DCPEN (SA09h: D6)
DCPLPFS (SA09h: D5)
DCPVEN (SA09h: D4)
DCP_TEST (SA09h: D3 to D0)
EXADINS (SA02h: D5)
CLK8OFF (SA07h: D4)
ST0S (SA07h: D1, D0)
ADCLKS (SA15h: D7, D6)
HIZEN (SA16h: D4)
PD64031A
PD64084
Correctly set the following registers when digitally connecting the PD64031A and PD64084 directly.
Also refer to the following table for register setting to specify whether the ghost reducer is used or not.
Register setting
Register
With Ghost Reducer
Used
1111
101
10
01
01
1
1
1
0
1
1
1
Table 14-2. Register Setting
Data Sheet S16021EJ2V0DS
10
0
1
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
With Ghost Reducer
Not Used
11
11
0
Digital data output setting
3-dimesnion processing prohibiting flag setting
20-MHz clock output setting
ADC input bias mode setting
Mode selection (WP1 pin control)
Digital clamp characteristic setting
Digital clamp selection
Error calculation block LPF selection
Clamp timing setting
Permissible error range during clamping
Internal ADC selection
8f
Clamp pulse output setting
ALTF clock delay setting
Digital input / output status select
SC
output setting
Remark
PD64084
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