UPD64084 NEC, UPD64084 Datasheet - Page 52

• Manufacturer Part Number: UPD64084
• Description: THREE-DIMENSIONAL Y/C SEPARATION LSI WITH ON-CHIP MEMORY
• Manufacturer: NEC

52
11
12
13
SA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3-D0
D7-D4
D3-D0
Bit
SHT1
Nonstandard signal
detection test bit
SHT0
Nonstandard signal
detection test bit
VCT
H / V counter test bit
OTT
H / V counter test bit
CLKG2D
Clock generator section
test bit
CLKGGT
Clock generator section
test bit
CLKGEB
Clock generator section
test bit
CLKGT
Clock generator section
test bit
HPLLFS
Specifies the horizontal
PLL filter.
BPLLFS
Specifies the burst PLL
filter.
FSCFG
Specifies the burst
extraction gain.
PLLFG
Specifies the PLL loop
gain.
KILR
Killer detection reference
HSSL
Horizontal sync slice
level
VSSL
Vertical sync slice level
Name and function
Table 15-2. Write Register Functions (12/14)
0: Normal mode
1: Test mode
0: Normal mode
1: Test mode
0: Normal mode
1: Test mode
0: Normal mode
1: Test mode
0: Test mode
1: Normal mode
0: Normal mode
1: Test mode
0: Normal mode
1: Test mode
0: Normal mode
1: Test mode
0: Slow convergence
1: Quick convergence
0: Quick convergence
1: Slow convergence
0: High gain
1: Low gain
0: Low gain (slow convergence)
1: High gain (quick convergence)
0000: Detection off
0001: Low detection sensitivity
1111: High detection sensitivity
0000: 4LSB
(in 8-bit input terms, 1LSB/step)
0000: HSSL setting + 0LSB
1111: HSSL setting + 15LSB
(in 8-bit input terms, 1LSB/step)
Data Sheet S16021EJ2V0DS
to
1111: 19LSB
Description
to
to
Typical
value
0010
1111
1000
PD64084
0
0
0
0
1
0
0
0
1
0
1
-
Initial
value
1010
1111
1000
0
0
0
0
1
0
0
0
1
1
0
1