AM79C983A Advanced Micro Devices, AM79C983A Datasheet - Page 41

• Manufacturer Part Number: AM79C983A
• Description: Integrated Multiport Repeater 2 (IMR2)
• Manufacturer: Advanced Micro Devices

the register jumps to the next level automatically. The data
format is as follows:
Note: The FIFO is emptied by reading. If the FIFO is
full, nothing more is recorded in Sample Error Status. If
the FIFO is empty (bit E = 0), there is nothing in the re-
maining 7 bytes; therefore, the next access will be the
first byte of the 8-byte register.
Report Packet Size
Address:
Report Packet Size is a two-byte register. The eleven
least significant bits are used. It sets the length of the
original packet (in octets) that is transmitted over the
Packet Report Port. The LS Byte is accessed first. The
limits are 14 bytes (binary 000000001110) and 1535
bytes (binary 10111111111). If the register is set at
less than 14, 14 bytes of the original packet are trans-
mitted over the Packet Reports Port. If the register is
set at greater than 1535 bytes, all of the original packet
is sent over the Packet Report Port.
STATS Control
Address:
STATS Control is a 1-byte register. It sets the operation
of the Packet Report Port and the RAUI port.
Byte 0
Byte 1
Byte 6
Byte 7
Byte 1
Byte 2
Byte 3
Byte 5
Byte 0
Byte 4
Bytes 2-7
bit 15
D Port Read/Write
bit 7
MSB
MSB
D Port Read/Write
bit 63
E
0
bit 23
E
N3-0
VL
DRE
RNT
S
L
A
FCS
1110 0011
1110 0100
0
VL
Very Long Event
Data Rate Error
Runt Packet
Short Event
Long Event
Alignment Error
FCS Error
Source Address. It is read low
Packet
Port Number
order byte to high order byte.
0
DRE
0
RNT S
1 - Valid
0 - Empty
N3
N2
L
P R E L I M I N A R Y
N1
A
bit 0
bit 8
LSB
N0
FCS
bit 16
bit 56
LSB
Am79C983A
T
F
Register Banks 16 through 30: Port Attribute
Registers
Port Attribute registers are accessed by writing the ap-
propriate port number into the C register, followed by
the attribute number. The table below shows the corre-
sponding register bank for each port.
Preferred Source Register, all registers are four bytes
long and read only unless special conditions are met.
The Last Source Address Register and the Preferred
Source Address Register are six bytes long and their
contents can be written and read.
Once the C Register is programmed with a valid port
and attribute number, the corresponding attribute is
transferred to a holding register upon reading the first
byte. Subsequent accesses to the D register access
the value in a least significant to most significant byte
order. During a read, once the last byte is read, the at-
tribute value is re-transferred to the holding register
and the sequence can be restarted.
When writing the Last Source Address Register and the
Preferred Source Register, if the sequence is aborted
prior to the 6th consecutive write cycle, the register value
is not altered. The sequence (read or write) may be
aborted and restarted by programming the C register.
Except for the Last Source Address Register and the
MSB
0
D Port Read/Write
Register Bank Access
0001 0000
0001 0001
0001 0010
0001 0011
0001 0100
0001 0101
0001 0110
0001 0111
0001 1000
0001 1001
0001 1010
0001 1011
0001 1100
0001 1101
0001 1110
T
0 Packet tagging is disabled
1 Packet tagging is enabled
0 Appending of a new FCS during port tag-
1 Appending of a new FCS during port tag-
ging is disabled
ging is enabled
F
0
0
Port
(activity recorded
10
RAUI
Expansion Bus
when MACEN
is TRUE)
8
9
11
AUI
0
1
2
3
4
5
6
7
0
0
0
LSB
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