AM79C983A Advanced Micro Devices, AM79C983A Datasheet - Page 39

• Manufacturer Part Number: AM79C983A
• Description: Integrated Multiport Repeater 2 (IMR2)
• Manufacturer: Advanced Micro Devices

Byte 0
Byte 1
Pn/AUI/RAUI/EP
Note: Setting a bit on this register invalidates the cor-
responding Source Address Changes Register.
Register Bank 4: Port Status Registers
These registers are accessed by writing 0000 0100 to
the C register.
Partitioning Status of Ports
Address:
These bits indicate the partition status of the corre-
sponding ports. Ports that are partitioned will transmit
packets. However, the IMR2 device will not repeat
packets received by a partitioned port.
Pn/AUI/RAUI
Link Test Status of Ports
Address:
The register bits indicate the Link Test Status of the cor-
responding ports. The bit setting is based on data re-
ceived by the QuIET device. Therefore, the bit setting is
invalid if a non-QuIET transceiver is used for the port.
TPn/SPn
Loopback Error Status
Address:
When a packet is transmitted, the DO signal is looped
back to the IMR2 device through the corresponding DI
pins. When a bit on this register is set, data is not being
looped back to the IMR2 device.
Pn/AUI/RAUI
Byte 0
Byte 1
Byte 0
Byte 1
TP7
SP3 SP2 SP1 SP0
D Port Read
MSB
D Port Read
D Port Read
MSB
P7
0
P7
0
MSB
1110 0000
1110 0010
1110 0011
TP6
P6
0
P6
0
1
0
0
1
TP5 TP4 TP3 TP2 TP1 TP0
0
1
1
0
P5
RAUI
P5
RAUI
Port partitioned
Port connected
No Loopback Error
Loopback Error
Last Source Address Lock
disabled
Last Source Address Lock
enabled
Link Test passed
Link Test failed
P4
AUI P11 P10 P9
P4
AUI P11 P10 P9
TP11
P3
P3
TP10
P2
P2
TP9 TP8
P R E L I M I N A R Y
P1
P1
LSB
LSB
P0
P8
P0
P8
LSB
Am79C983A
Byte 0
Byte 1
Note: The RAUI bit is not valid when the RAUI port is
in the reverse mode.
Receive Polarity Status
Address:
Each register bit represents the receive polarity status
of the corresponding port. The bit setting is based on
data received from the QuIET device through the serial
interface. If another transceiver device is used, the bit
setting reflects what is on the corresponding SDATA.
TPn/SPn
SQE Test Status
Address:
These register bits reflect the status of the last packet
received from the corresponding port. The RAUI bit is
not valid when the RAUI port is in the reverse mode.
Pn/AUI/RAUI
Register Bank 5: RMON Registers
The RMON registers can be accessed by writing to ad-
dress 0000 0101 and then accessing the individual reg-
isters. The RMON registers are 32-bit counters and
comply with etherStatsEntry of the statistics group of
the RMON MIB (RFC 1757) or etherHistoryEntry of the
History group of RFC 1757. They are 4 bytes long and
are read low order byte to high order byte.
The RMON registers can usually only be read. How-
ever, they can be written to when the Repeater Reset
bit or the Management Reset bit on the Device Config-
uration Register is set.
etherStatsOctets
Address:
The value in this register represents the total number of
octets received (excluding preamble bits, but including
FCS bits) by the IMR2 device.
etherStatsPkts
Address:
The value in this register represents the total number of
packets received by the IMR2 device.
Byte 0
Byte 1
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
SP3 SP2 SP1 SP0
MSB
D Port Read
D Port Read
MSB
P7
0
1110 0100
1110 0101
1110 0000
1110 0001
P6
0
0
1
0
1
P5
RAUI
No SQE Test Error
SQE Test Error
Polarity correct
Polarity reversed
P4
AUI P11 P10 P9
TP11 TP
P3
P2
10
TP9 TP8
P1
LSB
P0
P8
LSB
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