AM79C983A Advanced Micro Devices, AM79C983A Datasheet - Page 36

• Manufacturer Part Number: AM79C983A
• Description: Integrated Multiport Repeater 2 (IMR2)
• Manufacturer: Advanced Micro Devices

Multicast Address Pass Enable
Address:
Setting EP disables packet compression on packets
with multicast addresses.
EP
Note: Zeros should be written to all register bits ex-
cept the EP bit.
Data Rate Mismatch Interrupt Enable
Address:
The IMR2 device can generate an interrupt if received
data is outside the data rate tolerances. Setting a bit
enables the Data Rate Mismatch Interrupt control of
the corresponding port.
Pn/AUI/RAUI/EP
Last Source Address Compare Enable
Address:
Setting the EP bit in this register enables a comparison
of the destination address of an incoming packet to the
Last Source Address Register for the expansion port.
Packet compression is disabled when the destination
address matches the Last Source Address Register.
EP
36
Byte 0
Byte 1
Byte 0
Byte 1
Byte 0
Byte 1
MSB
D Port Read/Write
D Port Read/Write
MSB
D Port Read/Write
MSB
0
0
P7
0
0
0
1110 1001
1110 1010
1110 1100
0
EP
P6
EP
0
EP
0
1
0
1
0
0
P5
RAUI
0
0
0 Last Source Address Com-
1 Last
Data
Interrupt enabled
Data Rate Mismatch Interrupt
masked (disabled)
Compare enabled
Packet compression on pack-
ets with multicast addresses
is enabled
Packet compression on pack-
ets with multicast addresses
is disabled
pare masked (disabled)
0
0
P4
AUI P11 P10 P9
0
0
0
0
P3
0
0
Source
Rate
0
0
P2
0
0
P R E L I M I N A R Y
0
0
P1
0
0
Mismatch
Address
0
0
P0
P8
0
0
LSB
LSB
LSB
Am79C983A
Note: Zeros should be written to all register bits except
the EP bit.
Preferred Address Compare Enable
Address:
Setting the EP bit in this register enables a comparison
of the destination address of an incoming packet to the
Preferred Address Register for the expansion port.
Packet compression is disabled when the destination
address matches the Preferred Address Register.
EP
Note: Zeros should be written to all register bits except
the EP bit.
Transceiver Interface Changed Interrupt Enable
Address:
When a bit is set, an interrupt is generated if the device
connected to the corresponding port changes from a
QuIET device to a non-QuIET device or from a non-
QuIET device to a QuIET device.
Qn
Jabber Interrupt Enable
Address:
When a bit in this register is set, an indication of jabber
from a port will cause an interrupt.
TPn/SPn
Byte 0
Byte 1
Byte 0
Byte 1
X
MSB
D Port Read/Write
Transceiver 2
Transceiver 3
Transceiver 0
Transceiver 1
TP7
SP3 SP2 SP1 SP0
X
D Port Read/Write
MSB
1
0
MSB
D Port Read/Write
0
0
1110 1111
1111 0000
Device
masked (disabled)
Device Connection Changed Test enabled
1111 0001
TP6
X
0
EP
0
1 Preferred
TP5 TP4 TP3 TP2 TP1 TP0
0
0
X
0 Jabber Interrupt
1 Jabber Interrupt enabled
Connection
Compare enabled
Preferred
Compare disabled
PAUI [7:4]
PAUI [3:0]
PAUI [11:8]
AUI and RAUI ports
masked (disabled)
0
0
Q3
TP11 TP
0
0
Q2
Source
Source
Changed
0
0
10
Q1
TP9 TP8
0
0
Address
Address
LSB
Q0
LSB
0
0
LSB
Test