AM79C983A Advanced Micro Devices, AM79C983A Datasheet - Page 35

• Manufacturer Part Number: AM79C983A
• Description: Integrated Multiport Repeater 2 (IMR2)
• Manufacturer: Advanced Micro Devices

Byte 0
Byte 1
Byte 0
Byte 1
Pn/AUI/RAUI/EP
Link Status Change Interrupt Enable
Address:
Setting any of the bits in this register causes the INT pin
to be driven when there is a change in the Link Test
state of the corresponding port. The corresponding sta-
tus bit in the Link Test State Change Register is set to 1.
TPn/SPn
Loopback Error Change Interrupt Enable
Address:
Setting a bit in this register causes an interrupt to be
generated when the IMR2 device senses a change in the
Loop Back Error condition on the corresponding port.
Pn/AUI/RAUI
Polarity Change Interrupt Enable
Address:
Setting a bit in this register causes an interrupt to be gener-
ated when the polarity of the connected port is changed.
TPn/SPn
SQE Test Error Change Interrupt Enable
Address:
Byte 0
Byte 1
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
SP3 SP2 SP1 SP0
MSB
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
SP3 SP2 SP1 SP0
MSB
D Port Read/Write
D Port Read
D Port Read/Write
P7
0
MSB
1110 0010
1110 0011
1110 0100
1110 0101
P6
0
0
1 Loopback
0
1
0
1
Loopback Error Change Interrupt
P5
RAUI
masked (disabled)
Interrupt enabled
0 Runts with Valid FCS Interrupt
1 Runts
masked (disabled)
Link Status Change Interrupt
Link Status Change Interrupt
enabled
enabled
masked (disabled)
Interrupt enabled
masked (disabled)
Polarity
Polarity Change Interrupt
P4
AUI P11 P10 P9
TP11
TP11 TP
P3
with
Change
Error
TP10
P2
10
Valid
TP9 TP8
TP9 TP8
P R E L I M I N A R Y
P1
Interrupt
Change
LSB
LSB
P0
P8
LSB
FCS
Am79C983A
Setting a bit in this register causes an interrupt to be
generated when the IMR2 device senses a change in
the SQE Test Error condition at a port. This occurs
when an attached MAU has SQE Test enabled. A new
interrupt is generated when a condition change is
sensed by the IMR2 device.
Pn/AUI/RAUI
Source Address Changed Interrupt Enable
Address:
This register enables interrupts caused by a mismatch
between the source address of an incoming packet and
either the Last Source Address Register or the Preferred
Source Address Register. If Last Source Address Lock
is not set and the packet is a valid packet, a mismatch
between the source address and the Last Source
Address Register also causes the new source address
to be written into the Last Source Address Register.
Pn/AUI/RAUI/EP 0
Intruder Interrupt Enable
This register enables interrupts to be generated when the
source address of an incoming packet does not match the
Preferred Source Address Register on the corresponding
port. The corresponding interrupt can be interpreted as
an attempt by an intruder to gain access to the network.
The management system can then take appropriate ac-
tion, such as disabling the corresponding port.
Pn/AUI/RAUI
Address:
Byte 0
Byte 1
Byte 0
Byte 1
Byte 0
Byte 1
MSB
MSB
D Port Read/Write
D Port Read/Write
D Port Read/Write
P7
0
P7
0
P7
0
MSB
1110 0110
1110 0111
P6
0
P6
EP
P6
EP
1
0
1
0
1
Intruder Interrupt enabled
P5
RAUI
P5
RAUI
P5
RAUI
Intruder Interrupt masked (disabled)
Source
Interrupt masked (disabled)
Source
Interrupt enabled
SQE
Interrupt masked (disabled)
SQE
Interrupt enabled
P4
AUI P11 P10 P9
P4
AUI P11 P10 P9
P4
AUI P11 P10 P9
Test
Test
P3
P3
P3
Address
Address
P2
P2
P2
Error
Error
P1
P1
P1
Changed
Changed
Change
Change
P0
P8
LSB
P0
P8
P0
P8
LSB
LSB
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