AM79C873 Advanced Micro Devices, AM79C873 Datasheet - Page 18

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AM79C873

Manufacturer Part Number
AM79C873
Description
NetPHY -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
Manufacturer
Advanced Micro Devices
Datasheet

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supports, a connection will be automatically estab-
lished using that technology. This allows devices that
do not support Auto-Negotiation but support a common
mode of operation to establish a link.
MII Serial Management
The MII serial management interface consists of a data
interface, basic register set, and a serial management
interface to the register set. Through this interface it is
possible to control and configure multiple PHY devices,
get status and error information, and determine the
type and capabilities of the attached PHY device(s).
The NetPHY-1 devices management functions corre-
spond to MII specification for IEEE 802.3u-1995
(Clause 22) for registers 0 through 6 with vendor-spe-
cific registers 16,17, and 18.
In read/write operation, the management data frame is
64-bits long and starts with 32 contiguous logic one bits
18
MDIO Write
MDIO Read
MDC
MDC
Idle
Idle Preamble
32 "1"s
Preamble
32 "1"s
0
SFD
0
SFD
Figure 5. Management Interface - Read Frame Structure
Figure 6. Management Interface - Write Frame Structure
1
1
Op Code
0
1
Op Code
1
0
PHY Address
Write
P R E L I M I N A R Y
A4
A4
PHY Address
A3
A3
Am79C873
A0
A0
Register Address
Write
R4
Register Address
R4
(preamble) synchronization clock cycles on MDC. The
Start of Frame Delimiter (SFD) is indicated by a <01>
pattern followed by the operation code (OP):<10> indi-
cates Read operation and <01> indicates Write opera-
tion. For read operation, a 2-bit turnaround (TA) filing
between Register Address field and Data field is pro-
vided for MDIO to avoid contention. Following the turn-
around time, 16-bit data is read from or written onto
management registers.
Serial Management Interface
The serial control interface uses a simple two-wired se-
rial interface to obtain and control the status of the phys-
ical layer through the MII interface. The serial control
interface consists of Management Data Clock (MDC),
and Management Data Input/Output (MDI/O) signals.
The MDIO pin is bidirectional and may be shared by up
to 32 devices.
R3
R3
R0
R0
Turn Around
Z
Turn Around
1
0
D15
0
D14
D15
Read
Data
D14
Data
D1
D1
D0
D0
Idle
22164A-8
22164A-7
Idle

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