AM79C873 Advanced Micro Devices, AM79C873 Datasheet - Page 13

• Manufacturer Part Number: AM79C873
• Description: NetPHY -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
• Manufacturer: Advanced Micro Devices

100BASE Operation
The 100BASE transmitter receives 4-bit nibble data
clocked in at 25 MHz at the MII and outputs a scram-
bled 5-bit encoded MLT-3 signal to the media at 100
Mbps. The on-chip clock circuit converts the 25 MHz
clock into a 125 MHz clock for internal use.
The IEEE 802.3u specification defines the Media Inde-
pendent Interface. The interface specification defines a
dedicated receive data bus and a dedicated transmit
data bus.
CRS
CRS
TXD
TXD
RX_DV (receive data valid) input from the PHY to in-
dicate the PHY is presenting recovered and de-
coded nibbles to the MAC reconciliation sublayer. To
interpret a receive frame correctly by the reconcilia-
tion sublayer, RX_DV must encompass the frame
starting no later than the Start-of-Frame delimiter
and excluding any End-Stream delimiter.
RX_ER (receive error) transitions synchronously
with respect to RX_CLK. RX_ER will be asserted
Figure 2. Carrier Sense during 10BASE-T and 100BASE-TX Transmission
IDLE
SSD
J/K
Preamble
Preamble
P R E L I M I N A R Y
SFD
Am79C873
SFD
100Base-TX
10Base-T
These two busses include various controls and signal
indications that facilitate data transfers between the
NetPHY-1 device and the Reconciliation layer.
100BASE Transmit
The 100BASE transmitter consists of the functional
blocks shown in Figure 3. The 100BASE transmit sec-
tion converts 4-bit synchronous data provided by the
MII to a scrambled MLT-3 125 million symbols per sec-
ond serial data stream.
fo r 1 o r m o r e c l o ck p e r i o d s t o i n d i c a t e t o
the reconciliation sublayer that an error was
detected somewhere in the frame being transmit-
ted from the PHY to the reconciliation sublayer.
CRS (carrier sense) is asserted by the PHY when
either the transmit or receive medium is non-idle and
deasserted by the PHY when the transmit and receive
medium are idle. Figure 2 depicts the behavior of CRS
during 10BASE-T and 100BASE-TX transmission.
Data
Data
EFD
ESD
T/R
IDLE
22164A-4
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