AM79C873 Advanced Micro Devices, AM79C873 Datasheet - Page 11

• Manufacturer Part Number: AM79C873
• Description: NetPHY -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
• Manufacturer: Advanced Micro Devices

Clock Interface
OSCI/X1
Crystal or Oscillator Input
This pin should be connected to a 25 MHz (±50 ppm)
crystal if OSC/XTL=0 or a 25 MHz (±50 ppm) external
TTL oscillator input, if OSC/XTLB=1.
X2
Crystal Oscillator Output
An external 25 MHz (±50 ppm) crystal should be con-
nected to this pin if OSC/XTL=0, or left unconnected if
OSC/XTL=1.
OSC/XTL
Crystal or Oscillator Selector Pin
OSC/XTL=0: An external 25 MHz (±50ppm) crystal
should be connected to X1 and X2 pins.
CLK25M
25 MHz Clock Output
This clock is derived directly from the crystal circuit.
PHY Address Interface
The PHYAD[4:0] pins provide up to 32 unique PHY
addresses. An address selection of all zeros (00000)
will result in a PHY isolation condition. See the isolate
bit description in the BMCR, address 00.
PHYAD0
PHY Address 0
This pin provides PHY address bit 0 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 8 during power up/reset.
PHYAD1
PHY Address 1
This pin provides PHY address bit 1 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 7 during power up/reset.
PHYAD2
PHY Address 2
This pin provides PHY address bit 2 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 6 during power up/reset.
PHYAD3
PHY Address 3
This pin provides PHY address bit 3 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 5 during power up/reset.
OSC/XTL=1 : An external 25 MHz (±50ppm) oscilla-
tor should be connected to X1 and X2 should be left
unconnected.
P R E L I M I N A R Y
Output/Z
Input
Input
Input
Input
Input
Output
Output
Am79C873
PHYAD4
PHY Address 4
This pin provides PHY address bit 4 for multiple PHY
address applications. The status of this pin is latched
into Register 17, bit 4 during power up/reset.
Miscellaneous
NC
No Connect
These pins are to be left unconnected (floating).
BGREF
Bandgap Voltage Reference
Connect a 6.01K
the BGRET pin to provide an accurate current refer-
ence for the NetPHY-1 device.
BGRET
Bandgap Voltage Reference Return
This is the return pin for 6.01K
TRIDRV
Tri-State Digital Output
When set high, all digital output pins are set to a high
impedance state, and I/O pins, go to input mode.
RESET
Reset
This pin is the active low input that initializes the NetPHY-
1 device. It should remain low for 30 ms after VCC has
stabilized at 5 Vdc (nominal) before it transitions high.
TESTMODE
Test Mode Control Pin
TESTMODE=0: Normal operating mode.
TESTMODE=1: Enable test mode.
Power and Ground Pins
The power (VCC) and ground (GND) pins of the Net-
PHY-1 device are grouped in pairs of two categories -
Digital Circuitry Power/Ground Pairs and Analog Cir-
cuitry Power/Ground Pair.
DGND
Digital Logic Ground
These pins are the digital supply pairs.
DVCC
Digital Logic Power Supply
These pins are the digital supply pairs.
AGND
Analog Circuit Ground
These pins are the analog circuit supply pairs.
AVCC
Analog Circuit Power Supply
These pins are the analog circuit supply pairs.
, 1% resistor between this pin and
resistor connection.
Input
Input
Input
Input
Input
Power
Power
Power
Power
Input
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