AK4524VF Asahi Kasei Microsystems, AK4524VF Datasheet - Page 22

• Manufacturer Part Number: AK4524VF
• Description: 24BIT 96KHZ AUDIO CODEC
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
M0050-E-01
Addr
04H
05H
Addr
03H
DEM1-0: De-emphasis response (see Table 7)
ZTM1-0: Zero crossing time out period select (see Table 6)
ZCEI: ADC IPGA Zero crossing enable
SMUTE: DAC Input Soft Mute control
IPGL/R7-0: ADC Input Gain Level
00: 44.1kHz
01: OFF
10: 48kHz
11: 32kHz
0: Input PGA gain changes occur immediately
1: Input PGA gain changes occur only on zero-crossing or after timeout.
0: Normal operation
1: DAC outputs soft-muted
Register Name
Lch IPGA Control
Rch IPGA Control
Register Name
Deem and Volume Control
Initial: OFF
Initial: 1024fs
Initial: 1 (Enable)
The soft mute is independent of the output ATT and performed digitally.
RESET
Refer to Table 10
Initial: 7FH (0dB)
Digital ATT with 128 levels operates when writing data of less than 7FH. This ATT is a linear ATT with
8032 levels internally and these levels are assigned to pseudo-log data with 128 levels. The transition
between ATT values has 8032 levels and is done by soft changes. For example, when ATT changes from
127 to 126, the internal ATT value decreases from 8031 to 7775 one by one every fs cycles. It takes 8031
cycles (182ms@fs=44.1kHz) from 127 to 0 (Mute).
The IPGAs are set to “00H” when PD pin goes “L”. After returning to “H”, the IPGAs fade in the initial
value, “7FH” by 8031 cycles.
The IPGAs are set to “00H” when PWAD goes “0”. After returning to “1”, the IPGAs fade in the current
value. But the ADCs output “0” during first 516 cycles.
The IPAGs are set to “00H” when RSTAD goes “0”. After returning to “1”, the IPGAs fade in the current
value. But the ADCs output “0” during first 516 cycles.
RESET
SMUTE
IPGL7
IPGR7
D7
D7
0
0
IPGL6
IPGR6
D6
D6
1
0
0
- 22 -
IPGL5
IPGR5
D5
D5
1
0
0
IPGL4
IPGR4
ZCEI
D4
D4
1
1
IPGL3
IPGR3
ZTM1
D3
D3
1
1
ZTM0
IPGL2
IPGR2
D2
D2
0
1
DEM1
IPGL1
IPGR1
D1
D1
0
1
[AK4524]
DEM0
IPGL0
IPGR0
1999/5
D0
D0
1
1