AK4524VF Asahi Kasei Microsystems, AK4524VF Datasheet - Page 19

• Manufacturer Part Number: AK4524VF
• Description: 24BIT 96KHZ AUDIO CODEC
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
n Serial Control Interface
The internal registers are written by the 3 wire uP interface pins: CS, CCLK, CDTI. The data on this interface consists of
Chip address (2bits, C0/1) Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits).
Address and data is clocked in on the rising edge of CCLK. Data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CS. The operation of the control serial port may be completely asynchronous with the audio
sample rate. The maximum clock speed of the CCLK is 5MHz. The CS should be “H” or “L” if no access. The chip address
is fixed to “10”. Writing is invalid for the access to the chip address except for “10”. PD = “L” resets the registers to their
default values.
n Register Map
Note: For addresses from 08H to 1FH, data is not written.
M0050-E-01
Addr
00H
01H
02H
03H
04H
05H
06H
07H
PD = “L” resets the registers to their default values.
* READ command is not supported.
Power Down Control
Reset Control
Clock and Format Control
Deem and Volume Control
Lch IPGA Control
Rch IPGA Control
Lch ATT Control
Rch ATT Control
CS (CIF=1)
CS (CIF=0)
Register Name
CCLK
CDTI
C1 C0
0
1
C1-C0:
R/W:
A4-A0:
D7-D0:
SMUTE
IPGL7
IPGR7
R/W
DIF2
D7
2
0
0
0
0
A4
3
Figure 8. Control I/F Timing
A3
Chip Address (Fixed to “10”)
READ/WRITE (Fixed to “1”:WRITE)
Register Address
Control data
ATTL6
ATTR6
4
IPGL6
IPGR6
DIF1
D6
0
0
0
A2
5
A1 A0
6
- 19 -
ATTR5
ATTL5
IPGL5
IPGR5
DIF0
D5
7
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
8
CMODE
ATTR4
ATTL4
9
IPGL4
IPGR4
ZCEI
D4
0
0
10 11 12 13 14 15
ATTR3
ATTL3
IPGL3
IPGR3
ZTM1
CKS1
D3
0
0
ATTR2
ATTL2
PWVR
IPGL2
IPGR2
ZTM0
CKS0
D2
0
RSTAD
ATTR1
ATTL1
PWAD
DEM1
IPGL1
IPGR1
DFS1
D1
[AK4524]
RSTDA
ATTR0
ATTL0
DEM0
IPGL0
IPGR0
PEDA
DFS0
1999/5
D0