AK4524VF Asahi Kasei Microsystems, AK4524VF Datasheet - Page 17

• Manufacturer Part Number: AK4524VF
• Description: 24BIT 96KHZ AUDIO CODEC
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
n Power Down & Reset
The ADC and DAC of AK4524 are placed in the power-down mode by bringing a power down pin, PD “L” and each
digital filter is also reset at the same time. The internal register values are initialized by PD “L”. This reset should always
be done after power-up. And then as both control registers of ADC and DAC go reset state (RSTAD=RSTDA=”0”), each
register sholud be cancelled after doing the needed setting. In case of the ADC, an analog initialization cycle starts after
exiting the power-down or reset state. Therefore, the output data, SDTO becomes available after 516 cycles of LRCK
clock. This initialization cycle does not affect the DAC operation. Power down mode can be also controlled by the registers
(PWAD, PWDA).
M0050-E-01
Power Supply
RSTAD(register)
RSTDA(register)
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
IATT
SDTO
DAC Internal State
OATT
AOUT
External Mute
Example
External clocks
in slave mode
PD pin
· INITA:
· PD:
· XXH:
· FI:
· AOUT:
Initializing period of ADC analog section (516/fs).
Power down state. The contents of all registers are hold.
The current value in ATT register.
Fade in. After exiting power down and reset state, ATT value fades in.
Some pop noise may occur at “*”.
PD
PD
Reset INITA
*
00H
“0”
The clocks can be stopped.
00H
“0”
Figure 7. Reset & Power down sequence
Reset
00H ® XXH
MCLK, LRCK, BICK
FI
*
00H ® XXH
Normal
- 17 -
Output
FI
XXH
Normal
PD
00H 00H ® XXH
Output
XXH
“0”
INITA
FI
*
00H
“0”
Normal
XXH
Output
PD
*
00H ® XXH
Normal
FI
[AK4524]
XXH
1999/5