AK4524VF Asahi Kasei Microsystems, AK4524VF Datasheet - Page 15

• Manufacturer Part Number: AK4524VF
• Description: 24BIT 96KHZ AUDIO CODEC
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
n Input Volume
The AK4524 includes two channel independent analog volumes (IPGA) with 37 levels, 0.5dB step in front of ADC and
digital volumes (IATT) with 128 levels (including MUTE) after ADC. The control data of both volumes are assigned in the
same register address. When MSB of the register is “1”, the IPGA changes and the IATT changes at MSB “0”.
The IPGA is analog volumes and improves S/N compared with digital volume (Table 5). Level changes only occur during
zero-crossings to minimize switching noise. Zero-crossing detection is performed channel independently. If there is no
zero-crossings, then the level will change after a time-out. The time-out period (To) scales with fs. The periods of 256/fs,
512/fs, 1024/fs and 2048/fs are selectable by ZTM1-0 bits in normal speed mode. If new value is written to the IPGA
register before IPGA changes by zero-crossing or time-out, the previous value becomes invalid. And then the timer
(channel independent) for time-out is reset and the timer restarts for new IPGA value. Zero-crossing detection can be
enabled by ZCEI in the control register.
The IATT is a pseudo-log volume linear-interpolated internally. When changing the level, the transition between ATT
values has 8032 levels and is done by soft changes. Therefore, there is not any switching noise.
n Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at fs=44.1kHz and
also scales with sampling rate (fs).
n Output Volume
The Ak4524 includes digital volumes (OATT) with 128 levels (including MUTE) which have the same architecture as
IATT’s in front of DAC. T he OATT is a pseudo-log volume linear-interpolated internally. When changing the level, the
transition between ATT values has 8032 levels and is done by soft changes. Therefore, there is not any switching noise.
M0050-E-01
fs=44.1kHz, A-weight
ZTM1
0
0
1
1
Table 6. LRCK cycles for timeout period
ZTM0
0
1
0
1
Table 5. IPGA+ADC S/N
100dB
0dB
- 15 -
1024
2048
256
512
fsn
Input Gain Setting
+6dB
98dB
1024
2048
4096
512
fsd
+18dB
90dB
at reset
[AK4524]
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