SP301 Burr-Brown, SP301 Datasheet - Page 2

• Manufacturer Part Number: SP301
• Description: 12-Bit / 12MHz CCD/CIS SIGNAL PROCESSOR
• Manufacturer: Burr-Brown

SPECIFICATIONS
At T
PARAMETER
RESOLUTION
CONVERSION CHARACTERISTICS
ANALOG INPUTS
Full-Scale Input Range
Input Capacitance
External Reference Voltage Range
Reference Input Resistance
Input Limits
DYNAMIC CHARACTERISTICS
Integral Non-Linearity (INL)
Differential Non-Linearity (DNL)
No Missing Codes
Input-Referred Noise
PSRR
DIGITAL INPUTS
Logic Family
Convert Command
High Level Input Current (V
Low Level Input Current (V
Positive-Going Threshold Voltage
Negative-Going Threshold Voltage
Input Capacitance
DIGITAL OUTPUTS
Logic Family
Logic Coding
V
Output Voltage, V
Output Voltage, V
3-State Enable Time
3-State Enable Time
Output Capacitance
Data Latency
Data Output Delay
DC ACCURACY
Zero Error
Gain Error
POWER SUPPLY REQUIREMENTS
Supply Voltage: +V
Supply Current: +I
Power Dissipation
Thermal Resistance,
SPECIFIED TEMPERATURE RANGE
DRV
A
3-Channel CCD Mode
3-Channel CIS Mode
Low Level
High Level
Low Level
High Level
Low Level
High Level
= full specified temperature range, V
Supply Range
®
DRV
DRV
S
VSP3010
S
= +5V
= +3
JA
IN
IN
= 0V)
= V
DDD
)
DDA
= +5V, V
DDD
V
= +5V, f
Start Conversion
DDA
3-Channel Mode
1-Channel Mode
3-Channel Mode
1-Channel Mode
CONDITIONS
I
I
OE = HIGH
I
I
OL
OH
I
I
OE = LOW
C
OL
OH
OL
OH
Operating
= +5V 0.25V
L
= 1.6mA
= 0.5mA
= 50 A
= 50 A
= 15pF
= 50 A
= 50 A
ADCCK
= 6MHz, f
2
CK1
= 2MHz, f
GND
0.25
3.00
1.25
+2.7
+4.6
+2.4
+2.5
MIN
4.7
0.5
12
12
A
0
– 0.3
CK2
= 2MHz, and PGA gain = 1, unless otherwise specified.
Rising Edge of ADCCK
Straight Binary
VSP3010Y
CMOS
CMOS
TYP
0.04
3.40
1.65
800
100
500
410
100
0.3
0.3
0.8
1.5
12
10
12
20
82
5
2
5
6
5
1
V
DDA
MAX
1.75
0.75
3.80
2.05
+5.3
+0.1
+0.4
+0.1
108
540
450
+85
3.5
5.3
20
20
40
10
12
90
2
+ 0.3
Clock Cycles
LSBs rms
% FSR
UNITS
% FS
% FS
MHz
MHz
Vp-p
LSB
LSB
Bits
Bits
mW
mW
mA
C/W
mA
pF
pF
pF
ns
ns
ns
V
V
V
V
V
V
V
V
V
V
V
V
C
A
A