SP301 Burr-Brown, SP301 Datasheet - Page 13

• Manufacturer Part Number: SP301
• Description: 12-Bit / 12MHz CCD/CIS SIGNAL PROCESSOR
• Manufacturer: Burr-Brown

the bus coupling back high frequency noise. In addition,
resistors in series with each data line may help minimize the
surge current. Their use depends on the capacitive loading
seen by the converter. As the output levels change from low
to high and high to low, values in the range of 100 to 200
will limit the instantaneous current the output stage has to
provide for recharging the parasitic capacitances.
GROUNDING, BYPASSING, AND POWER SUPPLY
RECOMMENDATIONS
Proper grounding, bypassing, short lead length and the use
of ground planes are particularly important for high fre-
quency designs. Multi-layer PC boards are recommended
for the best performance since they offer distinct advantages
such as minimizing ground impedance, separation of signal
layers by ground layers, etc. It is recommended that analog
and digital ground pins of the VSP3010 be joined together
at the IC and connected only to the analog ground of the
system.
The VSP3010 has analog and digital supply pins, however,
the converter should be treated as an analog component and
all supply pins should be powered by the analog supply. This
will ensure the most consistent results since digital supply
lines often carry high levels of noise that would otherwise be
coupled into the converter and degrade the achievable per-
formance.
As the result of the high operation speed, the converter also
generates high frequency current transients and noise that
are fed back into the supply and reference lines. This
requires that the supply and reference pins be sufficiently
13
bypassed. Figure 3 shows the recommended decoupling
schemes for the entire chip. In most cases, 0.1 F ceramic
chip capacitors are adequate to keep the impedance low over
the wide frequency range. Their effectiveness largely de-
pends on the proximity to the individual supply pin.
When the VSP3010 is powered on, it will be initialized as a
3-channel CCD, 1V internal (2V full scale) reference mode
with analog gain of 1. This mode is commonly used for CCD
scanner applications. The calibration procedure is done at the
very beginning of the scan. Once calibration is done, regis-
ters on VSP3010 will keep this information (offset and gain
for each channel) during the operation.
To calibrate the VSP3010, use the following procedure:
Step 1: Set the VSP3010 to the proper mode.
Step 2: Set analog PGA gain to 1 (code: 00
Step 3: Scan a dark line.
Step 4: Calculate the pixel offsets according to the ADC
Step 5: Readjust input Offset Registers.
Step 6: Scan a white line.
Step 7: Calculate gain. It will be the ADC full scale divided
Step 8: Set the Gain Register. If the ADC output is not
0mV (code: C0
output.
by the ADC output when the white line is scanned.
close to full scale, go back to Step 3. The calibration
is complete if the output is close to full scale.
H
).
VSP3010
H
) and offset to
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