SP301 Burr-Brown, SP301 Datasheet - Page 12

• Manufacturer Part Number: SP301
• Description: 12-Bit / 12MHz CCD/CIS SIGNAL PROCESSOR
• Manufacturer: Burr-Brown

These Registers can be accessed by either the parallel or
serial port. In the parallel mode, the address and data port are
combined with the ADC data output pins. The data bus is
assigned as D0 to D7 (pin 25 to pin 32) and the address bus
is A0 to A2 (pin 33 to pin 35). In the serial mode, serial data
(SD), serial clock (SCLK), and write signal (WRT pin for
both parallel and serial writing) are assigned. The following
table shows how to access these modes.
Configuration Register
The Configuration Register is designed as follows:
resistance, V
difference between V
R
tolerable for V
properly.
where, I is 10nA, the typical leakage current of the VSP3010
input circuitry and t is the time between clamp pulses.
PROGRAMMING THE VSP3010
The VSP3010 consists of three CCD or CIS channels and a
12-bit A/D converter. Each channel (red, green, and blue) has
its own 8-bit offset and 5-bit gain adjustable registers to be
programmed by the user. There is also a 7-bit Configuration
Register on-chip to program the different operation modes.
These registers are as follows:
BIT
SW
D0
D1
D2
D3
D6
D7
A2
0
0
0
0
1
1
1
1
OE
0
0
1
1
is 4k
ADDRESS
3-Channel, D4 and D5 Disabled
R > G > B MUX Sequence
A1
0
0
1
1
0
0
1
1
P/S
0
1
0
1
Internal Reference
D
®
plus the driver’s impedance. 0.1V should be
CCD Mode
LOGIC ‘0’
V
ERROR
Reserved
A0
is the droop across C
0
1
0
1
0
1
0
1
VSP3010
REF
MODE
A/D Data Output Enabled, Serial Mode Enabled
Prohibit Mode
A/D Data Output Disabled, Serial Mode Enabled
A/D Data Output Disabled, Parallel Mode Enabled
C
= 1V
MIN
REGISTER
Configuration Register (7-Bit)
Red Channel Offset Register (8-Bit)
Green Channel Offset Register (8-Bit)
Blue Channel Offset Register (8-Bit)
Red Channel Gain Register (5-Bit)
Green Channel Gain Register (5-Bit)
Blue Channel Gain Reigster (5-Bit)
Reserved
S
and still keep the VSP3010 working
and V
= ( I/V
CLAMP
ERROR
1-Channel, D4 and D5 Enabled
B > G > R MUX Sequence
. The nominal value of
D4 D5
) • t
0
0
1
1
IN
External Reference
and V
V
0
1
0
1
LOGIC ‘1’
CIS Mode
Reserved
REF
= 1.5V
Red Channel
Green Channel
Blue Channel
Reserved
ERROR
is the
12
For Reading/Writing to the Configuration Register, the ad-
dress will be:
Example:
A 3-channel CCD with internal reference V
full-scale input), the mode will be:
For this example, V
Bypass V
reference mode is used.
Example:
A 1-channel CIS mode (red channel) with external 1.2V
reference:
= > D0 = ‘1’, D1 = X, D2 = ‘1’, D4 = ‘0’ and D5 = ‘0’
For this example, V
1.2V. This input will set the full-scale input of the VSP3010
at 2.4V.
Offset Registers
Offset registers control the analog offset input to the channel
prior to the PGA. There is an 8-bit Offset Register on each
channel. The offset range varies from –150mV to +50mV.
The Offset Register uses a Straight Binary code. All ‘0’s
correspond to –150mV and all ‘1’s correspond to +50mV of
the offset adjustment.
PGA Gain Registers
The PGA Gain Registers control the analog gain to the
channels prior to the A/D converter. There is a 5-bit PGA
Gain Register on each channel. The gain range varies from
1 to 4.44 (0dB to +13dB). The PGA Gain Register is a
Straight Binary code. All ‘0’s correspond to analog gain of
0dB and all ‘1’s correspond to the analog gain of 13dB.
OFFSET AND GAIN
CALIBRATION SEQUENCE
DIGITAL OUTPUTS
The digital outputs of the VSP3010 are designed to be
compatible with both high-speed TTL and CMOS logic
families. The driver stage of the digital outputs is supplied
through a separate supply pin, VDRV, which is not con-
nected to the analog supply pins. By adjusting the voltage on
VDRV, the digital output levels will vary respectively.
Thus, it is possible to operate the VSP3010 on a +5V analog
supply while interfacing the digital outputs to 3V logic.
It is recommended to keep the capacitive loading on the data
lines as low as possible (typically less than 15pF). Larger
capacitive loads demanding higher charging current surges
can feed back to the analog portion of the VSP3010 and
influence the performance. If necessary, external buffers or
latches may be used which provide the added benefit of
isolating the VSP3010 from any digital noise activities on
REF
= > D0 = ‘0’, D1 = ‘0’and D3 = ‘0’
A2 = ‘0’, A1 = ‘0’, and A0 = ‘0’
with 10 F and 0.1 F capacitors when internal
REF
REF
will be 1V.
will be an input pin, applied with
REF
= 1V (2V