SP301 Burr-Brown, SP301 Datasheet - Page 11

• Manufacturer Part Number: SP301
• Description: 12-Bit / 12MHz CCD/CIS SIGNAL PROCESSOR
• Manufacturer: Burr-Brown

In this mode, the CDS becomes a CIS signal processing
circuit (acting like a track-and-hold). Each CIS signal pro-
cessing circuit consists of a 5-bit PGA (0dB to +13dB) and
an 8-bit offset DAC (+50mV to –150mV). A 3-to-1 analog
MUX follows the CIS signal processing circuits and feeds a
high performance 12-bit A/D converter. The analog MUX is
not cycling between channels in this mode. Instead, the
analog MUX is connected to a specific channel, depending
on the data in the Configuration Register.
As specified in the “1-Channel CIS Mode” timing diagram,
the active period of CK1 (t
of ADCCK. If it is in the HIGH period of ADCCK, the
VSP3010 will not function properly.
ANALOG PGA
There is one analog PGA on each channel. Each analog PGA
is controlled by a 5-bit PGA gain register. The analog PGA
gain varies from 1 to 4.44 (0dB to +13dB). The transfer
function of the PGA is:
where X is the integer representation of the 5-bit PGA gain
register. Figure 1 shows the PGA transfer function plot.
FIGURE 1. PGA Transfer Function Plot.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
14
12
10
8
6
4
2
0
0
0
5
5
Gain = 4/(4 – 0.1 • X)
PGA TRANSFER FUNCTION
PGA TRANSFER FUNCTION
10
10
PGA Gain Setting
PGA Gain Setting
CK1B
15
15
) must be in the LOW period
20
20
25
25
31
31
11
CHOOSING AC INPUT COUPLING CAPACITORS
The purpose of the input coupling capacitor is to isolate the
DC output of the CCD array from affecting the VSP3010.
The internal clamping circuitry restores the necessary DC
component to the CCD output signal. The internal clamp
voltage, V
depends on the value of V
is 2.5V and if V
many factors that determine the size of the input coupling
capacitors including CCD signal swing, voltage droop across
the input capacitor since the last clamp interval, leakage
current of the VSP3010 input circuitry, and the time period
of CK1. Figure 2 shows a simplified equivalent circuit of the
VSP3010 inputs. In this equivalent circuit, the input cou-
pling capacitor, C
constructed as a capacitor divider (during CK1). For AC
analysis, op amp inputs are grounded. Therefore, the sam-
pling voltage, V
From this equation, we see that a larger value of C
V
attenuated less if C
tage to using a large value of C
more dummy or optical black pixels must be used to restore
the DC component of the input signal.
FIGURE 2. Equivalent Circuit of VSP3010 Inputs.
CHOOSING C
As mentioned previously, a large C
enough time for the CLP signal to charge up C
0.01 F to 0.1 F of C
to optimize C
calculate C
where, t
and N is the number of black pixels, R
S
closer to V
V
IN
C
CK1
MAX
CLP
CK1
CLAMP
MAX
is the time when both CK1 and CLP are HIGH
IN
IN
= ( t
C
, the following two equations can be used to
IN
V
. In other words, the input signal V
REF
MAX
and C
S
, is derived from the reference. V
S
(during CK1) is:
CK1
IN
IN
= (C
V
is set to 1.5V, V
, and the sampling capacitor, C
CLAMP
AND C
is large. However, there is a disadvan-
V
IN
MIN
S
• N)/[R
can be used for most cases. In order
IN
:
/C
REF
IN
MIN
; if V
SW
+ C
VSP3010
CK1
CK2
IN
• ln (V
REF
1
: the larger the C
IN
)) • V
CLAMP
is preferable if there is
is set to 1V, V
SW
4pF
4pF
C
C
D
1
2
IN
is the total switch
/V
is 3V. There are
ERROR
IN
AMP
OP
. Typically,
IN
IN
)]
will be
IN
makes
CLAMP
CLAMP
1
, are
, the
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