TE28F008xxx Intel Corporation, TE28F008xxx Datasheet - Page 23

• Manufacturer Part Number: TE28F008xxx
• Description: (TE28F Series) 3 Volt Advanced Boot Block Flash Memory
• Manufacturer: Intel Corporation

3.6.1
3.6.2
3.7
3UHOLPLQDU\
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RP# to the
system CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when V
both WE# and CE# must be low for a command write, driving either signal to V
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to V
By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
V
The CUI latches commands as issued by system software and is not altered by V
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
V
After any program or block erase operation is complete (even after V
V
flash memory array is desired.
Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling. System
designers should consider three supply current issues:
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor selection will suppress these transient voltage
peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each V
GND, and between its V
should be placed as close as possible to the package leads.
1. Standby current levels (I
2. Read current levels (I
3. Transient peaks produced by falling and rising edges of CE#.
CC
PPLK
CC
transitions above V
, V
), the CUI must be reset to read array mode via the Read Array command if access to the
PP
and RP# Transitions
28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
LKO
PP
CCR
and GND. These high-frequency, inherently low-inductance capacitors
CCS
(Lockout voltage), is read array mode.
)
)
IH
, regardless of the state of its control inputs.
CC
voltages are above V
PP
transitions down to
IH
PP
will inhibit
or CE#
LKO
. Since
CC
and
17